Taiwan semiconductor manufacturing company, ltd. (20240113089). SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF simplified abstract
Contents
- 1 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
Organization Name
taiwan semiconductor manufacturing company, ltd.
Inventor(s)
Po-Han Wang of Hsinchu City (TW)
Sih-Hao Liao of New Taipei City (TW)
Yu-Hsiang Hu of Hsinchu City (TW)
Hung-Jui Kuo of Hsinchu City (TW)
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240113089 titled 'SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
Simplified Explanation
The semiconductor package described in the patent application includes a die, an underfill layer, a patterned dielectric layer, and a plurality of conductive terminals. The die is encapsulated by the underfill layer, with the back surface of the die and the surface of the underfill layer being coplanar. The patterned dielectric layer is placed on the back surface of the die, and the conductive terminals are embedded in the patterned dielectric layer to be in contact with the die.
- Die encapsulated by underfill layer
- Back surface of die and underfill layer surface are coplanar
- Patterned dielectric layer on back surface of die
- Conductive terminals embedded in patterned dielectric layer
Potential Applications
The technology described in this patent application could be used in various semiconductor packaging applications, such as in microprocessors, memory chips, and other electronic devices where compact and efficient packaging is required.
Problems Solved
This technology solves the problem of ensuring proper electrical connections and thermal management in semiconductor packages. By embedding the conductive terminals in the patterned dielectric layer, a more reliable and compact packaging solution is achieved.
Benefits
The benefits of this technology include improved electrical performance, better thermal dissipation, and a more compact package design. Additionally, the coplanar arrangement of the die and underfill layer simplifies the manufacturing process and enhances the overall reliability of the semiconductor package.
Potential Commercial Applications
The technology described in this patent application could find commercial applications in the semiconductor industry, particularly in the production of high-performance electronic devices. Companies involved in the manufacturing of microprocessors, memory chips, and other semiconductor components could benefit from implementing this innovative packaging technology.
Possible Prior Art
One possible prior art for this technology could be the use of underfill layers in semiconductor packaging to improve reliability and thermal performance. However, the specific arrangement of the patterned dielectric layer and conductive terminals as described in this patent application may be a novel and non-obvious improvement in the field.
Original Abstract Submitted
a semiconductor package and a manufacturing method thereof are provided. the semiconductor package includes a die, an underfill layer, a patterned dielectric layer and a plurality of conductive terminals. the die has a front surface and a back surface opposite to the front surface. the underfill layer encapsulates the die, wherein a surface of the underfill layer and the back surface of the die are substantially coplanar to one another. the patterned dielectric layer is disposed on the back surface of the die. the conductive terminals are disposed on and in contact with a surface of the patterned dielectric layer and partially embedded in the patterned dielectric layer to be in contact with the die, wherein a portion of the surface of the patterned dielectric layer that directly under each of the conductive terminals is substantially parallel with the back surface of the die.
