Taiwan semiconductor manufacturing company, ltd. (20240105516). ASYMMETRIC SOURCE/DRAIN EPITAXY simplified abstract

From WikiPatents
Jump to navigation Jump to search

ASYMMETRIC SOURCE/DRAIN EPITAXY

Organization Name

taiwan semiconductor manufacturing company, ltd.

Inventor(s)

Yu-Lien Huang of Jhubei (TW)

ASYMMETRIC SOURCE/DRAIN EPITAXY - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240105516 titled 'ASYMMETRIC SOURCE/DRAIN EPITAXY

Simplified Explanation

The patent application describes a method for forming source/drain epitaxy on a plurality of fins in a semiconductor device, where the epitaxy on each fin is asymmetrically recessed. This results in a first epitaxy on one fin being higher than the second epitaxy on another fin.

  • Formation of fins and dummy gate structure on a substrate
  • Deposition of spacer layer over the fins and dummy gate structure
  • Recessing the spacer layer to form asymmetrically recessed spacers along fin sidewalls
  • Growing source/drain epitaxy on exposed fin portions, with asymmetrical heights on different fins

Potential Applications

This technology can be applied in the manufacturing of advanced semiconductor devices, such as high-performance transistors and integrated circuits.

Problems Solved

1. Improved control over source/drain epitaxy growth on fins 2. Enhanced device performance through asymmetrical epitaxy heights

Benefits

1. Increased device efficiency and speed 2. Better integration of source/drain regions with the fin structure 3. Potential for higher transistor density on a chip

Potential Commercial Applications

"Enhanced Source/Drain Epitaxy Growth for Semiconductor Devices"

Possible Prior Art

Prior art may include patents or publications related to epitaxy growth techniques on semiconductor fins, particularly focusing on asymmetrical epitaxy heights.

Unanswered Questions

How does this technology impact overall device power consumption?

The article does not address the potential impact of this technology on the power efficiency of semiconductor devices. This could be a crucial factor in determining the practicality and widespread adoption of the innovation.

What are the potential challenges in scaling up this technology for mass production?

The article does not discuss the scalability of the proposed method for large-scale manufacturing. Understanding the challenges and limitations in scaling up this technology is essential for its successful commercialization.


Original Abstract Submitted

a method includes forming a plurality of fins on a substrate and a dummy gate structure over the fins. a spacer layer is formed over the dummy gate structure and the fins. the spacer layer is recessed to form asymmetrically recessed spacers along sidewalls of each of the fins, thereby exposing a portion of each of the fins. a source/drain epitaxy is grown on the exposed portions of the plurality of fins, a first source/drain epitaxy on a first fin being asymmetrical to a second source/drain epitaxy on a second fin. a device includes a first and second fin on a substrate with a gate structure formed over the first and second fins. an epitaxy if formed over the first fin and the second fin on the same side of the gate structure, where the height of the first epitaxy is greater than the height of the second epitaxy.