Taiwan semiconductor manufacturing co., ltd. (20240128143). PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME simplified abstract
Contents
- 1 PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME
Organization Name
taiwan semiconductor manufacturing co., ltd.
Inventor(s)
Chia-Han Hsieh of Miaoli County (TW)
Yu-Jin Hu of Taoyuan City (TW)
Hua-Wei Tseng of New Taipei City (TW)
An-Jhih Su of Taoyuan City (TW)
Der-Chyang Yeh of Hsin-chu (TW)
PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240128143 titled 'PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME
Simplified Explanation
The method described in the abstract involves forming a package structure by performing various processes such as laser grooving, forming a protective layer, patterning the protective layer, planarization, and mechanical dicing.
- Interconnect structure formed on a substrate
- Laser grooving process to create a first opening and a debris layer
- Formation of a protective layer to cover the first opening and debris layer
- Patterning the protective layer to create a second opening
- Planarization process to expose the topmost contact pad
- Mechanical dicing process through the second opening to cut the substrate into semiconductor dies
Potential Applications
This technology can be applied in the semiconductor industry for the manufacturing of integrated circuits and electronic devices.
Problems Solved
This technology helps in improving the efficiency and precision of forming package structures in semiconductor devices.
Benefits
The method described in the patent application can lead to enhanced performance and reliability of semiconductor devices by ensuring proper formation of package structures.
Potential Commercial Applications
"Advanced Package Structure Formation Method for Semiconductor Devices"
Possible Prior Art
There may be prior art related to laser grooving processes, protective layer formation, and planarization techniques in semiconductor device manufacturing.
Unanswered Questions
How does this method compare to traditional package structure formation techniques?
The article does not provide a comparison between this method and traditional techniques in terms of efficiency, cost, and quality.
What are the specific parameters and requirements for each step of the method?
The article does not detail the specific parameters or conditions needed for the laser grooving, protective layer formation, and planarization processes.
Original Abstract Submitted
provided are a package structure and a method of forming the same. the method includes: forming an interconnect structure on a substrate; performing a laser grooving process to form a first opening in the interconnect structure and form a debris layer on a sidewall of the first opening in a same step; forming a protective layer to fill in the first opening and cover the debris layer and the interconnect structure; patterning the protective layer to form a second opening, wherein the second opening is spaced from the debris layer by the protective layer; performing a planarization process on the protective layer to expose a topmost contact pad of the interconnect structure; and performing a mechanical dicing process through the second opening to form a third opening in the substrate and cut the substrate into a plurality of semiconductor dies.
