Taiwan semiconductor manufacturing co., ltd. (20240128122). SEMICONDUCTOR PACKAGE simplified abstract

SEMICONDUCTOR PACKAGE

Organization Name

taiwan semiconductor manufacturing co., ltd.

Inventor(s)

Wei-Chung Chang of Hsinchu (TW)

Ming-Che Ho of Tainan City (TW)

Hung-Jui Kuo of Hsinchu City (TW)

SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240128122 titled 'SEMICONDUCTOR PACKAGE

Simplified Explanation

The semiconductor package described in the patent application includes a substrate with a through hole, first and second barrier layers, routing via, first and second routing patterns, and a semiconductor die. The substrate has a tapered profile through hole, wider at the frontside surface than at the backside surface. The first barrier layer extends on the backside surface, while the second barrier layer extends along the sidewalls of the through hole and on the frontside surface. The routing via fills the through hole and is separated from the sidewalls by the second barrier layer. The first routing pattern extends over the first barrier layer and the routing via, electrically connected to the end of the routing via. The second routing pattern extends over the second barrier layer on the frontside surface, directly contacting the other end of the routing via, which is electrically connected to the semiconductor die.

• Substrate with tapered profile through hole
• First and second barrier layers for protection and isolation
• Routing via filling the through hole
• First routing pattern electrically connected to one end of the routing via
• Second routing pattern directly contacting the other end of the routing via
• Semiconductor die electrically connected to the routing via

Potential Applications

The technology described in the patent application could be applied in the manufacturing of advanced semiconductor packages for various electronic devices such as smartphones, tablets, and computers.

Problems Solved

This technology solves the problem of ensuring proper electrical connections between the semiconductor die and the substrate in a semiconductor package, while also providing protection and isolation for the routing via.

Benefits

The benefits of this technology include improved reliability and performance of semiconductor packages, as well as potentially reducing manufacturing costs by simplifying the assembly process.

Potential Commercial Applications

"Advanced Semiconductor Package Technology for Electronic Devices"

Possible Prior Art

There may be prior art related to semiconductor packaging technologies that involve routing vias and barrier layers for protection and isolation, but specific examples would need to be researched further.

How does this technology compare to existing semiconductor packaging solutions in terms of performance and reliability?

The article does not provide a direct comparison with existing semiconductor packaging solutions, so it is unclear how this technology stacks up against current industry standards.

What are the potential challenges or limitations of implementing this technology in mass production?

The article does not address any potential challenges or limitations that may arise when implementing this technology in mass production, leaving room for further exploration into the practical aspects of its commercialization.

Original Abstract Submitted

semiconductor package includes substrate, first barrier layer, second barrier layer, routing via, first routing pattern, second routing pattern, semiconductor die. substrate has through hole with tapered profile, wider at frontside surface than at backside surface of substrate. first barrier layer extends on backside surface. second barrier layer extends along sidewalls of through hole and on frontside surface. routing via fills through hole and is separated from sidewalls of through hole by at least second barrier layer. first routing pattern extends over first barrier layer on backside surface and over routing via. first routing pattern is electrically connected to end of routing via and has protrusion protruding towards end of routing via in correspondence of through hole. second routing pattern extends over second barrier layer on frontside surface. second routing pattern directly contacts another end of routing via. semiconductor die is electrically connected to routing via by first routing pattern.