View source for Taiwan semiconductor manufacturing co., ltd. (20240096830). Adding Sealing Material to Wafer edge for Wafer Bonding simplified abstract

=Adding Sealing Material to Wafer edge for Wafer Bonding=


==Organization Name==

[[:Category:taiwan semiconductor manufacturing co., ltd.|taiwan semiconductor manufacturing co., ltd.]]


[[Category:taiwan semiconductor manufacturing co., ltd.]]

==Inventor(s)==

[[:Category:Yu-Yi Huang of Taipei City (TW)|Yu-Yi Huang of Taipei City (TW)]][[Category:Yu-Yi Huang of Taipei City (TW)]]

[[:Category:Yu-Hung Lin of Taichung City (TW)|Yu-Hung Lin of Taichung City (TW)]][[Category:Yu-Hung Lin of Taichung City (TW)]]

[[:Category:Wei-Ming Wang of Taichung City (TW)|Wei-Ming Wang of Taichung City (TW)]][[Category:Wei-Ming Wang of Taichung City (TW)]]

[[:Category:Chen Chen of New Taipei City (TW)|Chen Chen of New Taipei City (TW)]][[Category:Chen Chen of New Taipei City (TW)]]

[[:Category:Shih-Peng Tai of Xinpu Township (TW)|Shih-Peng Tai of Xinpu Township (TW)]][[Category:Shih-Peng Tai of Xinpu Township (TW)]]

[[:Category:Kuo-Chung Yee of Taoyuan City (TW)|Kuo-Chung Yee of Taoyuan City (TW)]][[Category:Kuo-Chung Yee of Taoyuan City (TW)]]

==Adding Sealing Material to Wafer edge for Wafer Bonding - A simplified explanation of the abstract==


This abstract first appeared for US patent application 20240096830 titled 'Adding Sealing Material to Wafer edge for Wafer Bonding

==Simplified Explanation==

The method described in the patent application involves forming a sealing layer at the edge region of a wafer, bonding it to another wafer to create a wafer stack, performing an edge trimming process, and leaving a portion of the sealing layer in the stack. An interconnect structure with redistribution lines connected to integrated circuit devices is then formed in the second wafer.

* Sealing layer formed at edge region of first wafer
* First wafer bonded to second wafer to create wafer stack
* Edge trimming process performed on wafer stack
* Portion of sealing layer left in wafer stack
* Interconnect structure with redistribution lines formed in second wafer

== Potential Applications ==
This technology could be applied in the semiconductor industry for the manufacturing of integrated circuits and electronic devices.

== Problems Solved ==
1. Improved bonding process between wafers
2. Enhanced interconnect structure for integrated circuit devices

== Benefits ==
1. Increased reliability of wafer bonding
2. Higher performance of integrated circuit devices
3. Cost-effective manufacturing process

== Potential Commercial Applications ==
Optimizing Wafer Bonding Process for Enhanced Interconnect Structures

== Possible Prior Art ==
There are existing methods for wafer bonding and interconnect structure formation in the semiconductor industry, but this specific combination of steps may be novel.

== Unanswered Questions ==
=== How does the edge trimming process affect the overall performance of the wafer stack? ===
The article does not provide details on the impact of the edge trimming process on the functionality of the wafer stack.

=== What are the specific materials used for the sealing layer and how do they contribute to the bonding process? ===
The patent application does not specify the materials used for the sealing layer and their role in the bonding process.


==Original Abstract Submitted==

a method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. at a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. an edge trimming process is then performed on the wafer stack. after the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. an interconnect structure is formed as a part of the second wafer. the interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.



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