Taiwan Semiconductor Manufacturing Company, Ltd. patent applications published on April 25th, 2024
Contents
- 1 Patent applications for Taiwan Semiconductor Manufacturing Company, Ltd. on April 25th, 2024
- 1.1 BioFET SYSTEM (18403362)
- 1.2 TESTING MODULE AND TESTING METHOD USING THE SAME (18402740)
- 1.3 SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS (18403623)
- 1.4 EUV PHOTO MASKS AND MANUFACTURING METHOD THEREOF (18402511)
- 1.5 LITHOGRAPHY MASK (18402957)
- 1.6 PHOTORESIST AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE (18190917)
- 1.7 SYSTEM AND METHOD FOR THERMAL MANAGEMENT OF RETICLE IN SEMICONDUCTOR MANUFACTURING (18401729)
- 1.8 Circuit Synthesis Optimization for Implements on Integrated Circuit (18403924)
- 1.9 Write Driver Boost Circuit for Memory Cells (18402172)
- 1.10 METHOD AND MEMORY DEVICE WITH INCREASED READ AND WRITE MARGIN (18402647)
- 1.11 INTEGRATED STEALTH LASER FOR WAFER EDGE TRIMMING PROCESS (18402991)
- 1.12 METHOD OF BREAKING THROUGH ETCH STOP LAYER (18402563)
- 1.13 METHOD FOR FORMING AND USING MASK (18401800)
- 1.14 FIN FIELD-EFFECT TRANSISTOR DEVICE AND METHOD OF FORMING THE SAME (18402018)
- 1.15 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MANUFACTURING METHOD THEREOF (18099357)
- 1.16 PHOTONIC INTEGRATED PACKAGE AND METHOD FORMING SAME (18401811)
- 1.17 MODULAR PRESSURIZED WORKSTATION (18403613)
- 1.18 Shallow Trench Isolation Forming Method and Structures Resulting Therefrom (18401955)
- 1.19 INTERCONNECT STRUCUTRE WITH PROTECTIVE ETCH-STOP (18403044)
- 1.20 Different Isolation Liners for Different Type FinFETs and Associated Isolation Feature Fabrication (18543934)
- 1.21 SEMICONDUCTOR DEVICE PRE-CLEANING (18401989)
- 1.22 Barrier-Free Approach for Forming Contact Plugs (18402859)
- 1.23 Ion Implantation For Nano-FET (18401780)
- 1.24 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (18403686)
- 1.25 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (18403763)
- 1.26 Conductive Traces in Semiconductor Devices and Methods of Forming Same (18401815)
- 1.27 LOW-STRESS PASSIVATION LAYER (18153912)
- 1.28 PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME (18162679)
- 1.29 SEMICONDUCTOR PACKAGES AND METHOD OF MANUFACTURE (18401928)
- 1.30 SEMICONDUCTOR PACKAGES HAVING CONDUCTIVE PILLARS WITH INCLINED SURFACES (18402611)
- 1.31 SUBSTRATE AND PACKAGE STRUCTURE (18403560)
- 1.32 SEMICONDUCTOR MANUFACTURING METHOD (18099097)
- 1.33 SEMICONDUCTOR DIE PACKAGE AND METHODS OF FORMATION (18302466)
- 1.34 SEMICONDUCTOR DEVICE (18402734)
- 1.35 HIGH VOLTAGE DEVICE WITH GATE EXTENSIONS (18403076)
- 1.36 PASSIVATION LAYER FOR EPITAXIAL SEMICONDUCTOR PROCESS (18405099)
- 1.37 SEMICONDUCTOR DEVICE (18403495)
- 1.38 SEMICONDUCTOR STRUCTURE WITH NITRIDED INNER SPACERS AND METHOD FOR MANUFACTURING THE SAME (18154614)
- 1.39 Semiconductor Device and Method (18401833)
- 1.40 INNER SPACERS FOR GATE-ALL-AROUND SEMICONDUCTOR DEVICES (18395058)
- 1.41 SEMICONDUCTOR DEVICE AND MEHTOD OF FABRICATING THE SAME (18164600)
- 1.42 MEMORY CELL STRUCTURE (18405160)
- 1.43 THREE-DIMENSIONAL MEMORY DEVICE AND METHOD (18401988)
- 1.44 FERROELECTRIC MEMORY DEVICE AND MEMORY ARRAY (18178529)
- 1.45 SEMICONDUCTOR DEVICE WITH STACKED MEMORY PERIPHERY AND ARRAY AND METHOD FOR FORMING THE SAME (18178371)
- 1.46 RESISTIVE MEMORY CELL WITH SWITCHING LAYER COMPRISING ONE OR MORE DOPANTS (18403014)
Patent applications for Taiwan Semiconductor Manufacturing Company, Ltd. on April 25th, 2024
BioFET SYSTEM (18403362)
Main Inventor
Yu-Jie Huang
TESTING MODULE AND TESTING METHOD USING THE SAME (18402740)
Main Inventor
Hao Chen
SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS (18403623)
Main Inventor
Sandeep Kumar GOEL
EUV PHOTO MASKS AND MANUFACTURING METHOD THEREOF (18402511)
Main Inventor
Yun-Yue LIN
LITHOGRAPHY MASK (18402957)
Main Inventor
Chien-Cheng Chen
PHOTORESIST AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE (18190917)
Main Inventor
Chieh-Hsin HSIEH
SYSTEM AND METHOD FOR THERMAL MANAGEMENT OF RETICLE IN SEMICONDUCTOR MANUFACTURING (18401729)
Main Inventor
Yueh-Lin Yang
Circuit Synthesis Optimization for Implements on Integrated Circuit (18403924)
Main Inventor
Chao-Chun Lo
Write Driver Boost Circuit for Memory Cells (18402172)
Main Inventor
Sanjeev Kumar Jain
METHOD AND MEMORY DEVICE WITH INCREASED READ AND WRITE MARGIN (18402647)
Main Inventor
Hung-Chang Yu
INTEGRATED STEALTH LASER FOR WAFER EDGE TRIMMING PROCESS (18402991)
Main Inventor
Ming-Tung Wu
METHOD OF BREAKING THROUGH ETCH STOP LAYER (18402563)
Main Inventor
Yu-Shih Wang
METHOD FOR FORMING AND USING MASK (18401800)
Main Inventor
Ching-Yu Chang
FIN FIELD-EFFECT TRANSISTOR DEVICE AND METHOD OF FORMING THE SAME (18402018)
Main Inventor
Min-Hsiu Hung
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MANUFACTURING METHOD THEREOF (18099357)
Main Inventor
Yung-Chi LIN
PHOTONIC INTEGRATED PACKAGE AND METHOD FORMING SAME (18401811)
Main Inventor
Chen-Hua Yu
MODULAR PRESSURIZED WORKSTATION (18403613)
Main Inventor
Chun-Jung HUANG
Shallow Trench Isolation Forming Method and Structures Resulting Therefrom (18401955)
Main Inventor
Szu-Ying Chen
INTERCONNECT STRUCUTRE WITH PROTECTIVE ETCH-STOP (18403044)
Main Inventor
Shao-Kuan Lee
Different Isolation Liners for Different Type FinFETs and Associated Isolation Feature Fabrication (18543934)
Main Inventor
Tzung-Yi TSAI
SEMICONDUCTOR DEVICE PRE-CLEANING (18401989)
Main Inventor
Li-Wei CHU
Barrier-Free Approach for Forming Contact Plugs (18402859)
Main Inventor
Ching-Yi Chen
Ion Implantation For Nano-FET (18401780)
Main Inventor
Yu-Chang Lin
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (18403686)
Main Inventor
Shu-Shen Yeh
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (18403763)
Main Inventor
Chung-Jung Wu
Conductive Traces in Semiconductor Devices and Methods of Forming Same (18401815)
Main Inventor
Chao-Wen Shih
LOW-STRESS PASSIVATION LAYER (18153912)
Main Inventor
Hsiang-Ku SHEN
PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME (18162679)
Main Inventor
Chih-Wei Wu
SEMICONDUCTOR PACKAGES AND METHOD OF MANUFACTURE (18401928)
Main Inventor
Wei-Yu Chen
SEMICONDUCTOR PACKAGES HAVING CONDUCTIVE PILLARS WITH INCLINED SURFACES (18402611)
Main Inventor
Chiang-Jui Chu
SUBSTRATE AND PACKAGE STRUCTURE (18403560)
Main Inventor
Wei-Hung Lin
SEMICONDUCTOR MANUFACTURING METHOD (18099097)
Main Inventor
Wen-Chih CHIOU
SEMICONDUCTOR DIE PACKAGE AND METHODS OF FORMATION (18302466)
Main Inventor
Chien Hung LIU
SEMICONDUCTOR DEVICE (18402734)
Main Inventor
Yu-Chien Ku
HIGH VOLTAGE DEVICE WITH GATE EXTENSIONS (18403076)
Main Inventor
Jhih-Bin Chen
PASSIVATION LAYER FOR EPITAXIAL SEMICONDUCTOR PROCESS (18405099)
Main Inventor
Yin-Kai Liao
SEMICONDUCTOR DEVICE (18403495)
Main Inventor
Shih-Cheng CHEN
SEMICONDUCTOR STRUCTURE WITH NITRIDED INNER SPACERS AND METHOD FOR MANUFACTURING THE SAME (18154614)
Main Inventor
Man-Nung SU
Semiconductor Device and Method (18401833)
Main Inventor
Wen-Kai Lin
INNER SPACERS FOR GATE-ALL-AROUND SEMICONDUCTOR DEVICES (18395058)
Main Inventor
Yu-Yun Peng
SEMICONDUCTOR DEVICE AND MEHTOD OF FABRICATING THE SAME (18164600)
Main Inventor
Ken-Ichi Goto
MEMORY CELL STRUCTURE (18405160)
Main Inventor
Jhon Jhy LIAW
THREE-DIMENSIONAL MEMORY DEVICE AND METHOD (18401988)
Main Inventor
Feng-Cheng Yang
FERROELECTRIC MEMORY DEVICE AND MEMORY ARRAY (18178529)
Main Inventor
Meng-Han Lin
SEMICONDUCTOR DEVICE WITH STACKED MEMORY PERIPHERY AND ARRAY AND METHOD FOR FORMING THE SAME (18178371)
Main Inventor
Han-Jong CHIA
RESISTIVE MEMORY CELL WITH SWITCHING LAYER COMPRISING ONE OR MORE DOPANTS (18403014)
Main Inventor
Fa-Shen Jiang
