Difference between revisions of "TEXAS INSTRUMENTS INCORPORATED patent applications published on November 30th, 2023"
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==Patent applications for TEXAS INSTRUMENTS INCORPORATED on November 30th, 2023== | ==Patent applications for TEXAS INSTRUMENTS INCORPORATED on November 30th, 2023== | ||
− | ===QUICK TURN OFF OF CONTACTOR SYSTEM DURING POWER OFF ([[US Patent Application 17826822. QUICK TURN OFF OF CONTACTOR SYSTEM DURING POWER OFF simplified abstract|17826822]])=== | + | ===QUICK TURN OFF OF CONTACTOR SYSTEM DURING POWER OFF ([[US Patent Application 17826822. QUICK TURN OFF OF CONTACTOR SYSTEM DURING POWER OFF simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|17826822]])=== |
Line 42: | Line 9: | ||
− | ===SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS ([[US Patent Application 18234003. SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS simplified abstract|18234003]])=== | + | ===SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS ([[US Patent Application 18234003. SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|18234003]])=== |
Line 50: | Line 17: | ||
− | ===FSM BASED CLOCK SWITCHING OF ASYNCHRONOUS CLOCKS ([[US Patent Application 17824695. FSM BASED CLOCK SWITCHING OF ASYNCHRONOUS CLOCKS simplified abstract|17824695]])=== | + | ===FSM BASED CLOCK SWITCHING OF ASYNCHRONOUS CLOCKS ([[US Patent Application 17824695. FSM BASED CLOCK SWITCHING OF ASYNCHRONOUS CLOCKS simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|17824695]])=== |
Line 58: | Line 25: | ||
− | ===STATIC POWER REDUCTION IN CACHES USING DETERMINISTIC NAPS ([[US Patent Application 18450079. STATIC POWER REDUCTION IN CACHES USING DETERMINISTIC NAPS simplified abstract|18450079]])=== | + | ===STATIC POWER REDUCTION IN CACHES USING DETERMINISTIC NAPS ([[US Patent Application 18450079. STATIC POWER REDUCTION IN CACHES USING DETERMINISTIC NAPS simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|18450079]])=== |
Line 66: | Line 33: | ||
− | ===CONFIGURABLE CACHE FOR COHERENT SYSTEM ([[US Patent Application 18229814. CONFIGURABLE CACHE FOR COHERENT SYSTEM simplified abstract|18229814]])=== | + | ===CONFIGURABLE CACHE FOR COHERENT SYSTEM ([[US Patent Application 18229814. CONFIGURABLE CACHE FOR COHERENT SYSTEM simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|18229814]])=== |
Line 74: | Line 41: | ||
− | ===STREAMING ENGINE WITH EARLY EXIT FROM LOOP LEVELS SUPPORTING EARLY EXIT LOOPS AND IRREGULAR LOOPS ([[US Patent Application 18361985. STREAMING ENGINE WITH EARLY EXIT FROM LOOP LEVELS SUPPORTING EARLY EXIT LOOPS AND IRREGULAR LOOPS simplified abstract|18361985]])=== | + | ===STREAMING ENGINE WITH EARLY EXIT FROM LOOP LEVELS SUPPORTING EARLY EXIT LOOPS AND IRREGULAR LOOPS ([[US Patent Application 18361985. STREAMING ENGINE WITH EARLY EXIT FROM LOOP LEVELS SUPPORTING EARLY EXIT LOOPS AND IRREGULAR LOOPS simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|18361985]])=== |
Line 82: | Line 49: | ||
− | ===HARDWARE EVENT TRIGGERED PIPELINE CONTROL ([[US Patent Application 18175364. HARDWARE EVENT TRIGGERED PIPELINE CONTROL simplified abstract|18175364]])=== | + | ===HARDWARE EVENT TRIGGERED PIPELINE CONTROL ([[US Patent Application 18175364. HARDWARE EVENT TRIGGERED PIPELINE CONTROL simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|18175364]])=== |
Line 90: | Line 57: | ||
− | ===RESOURCE AVAILABILITY MANAGEMENT USING REAL-TIME TASK MANAGER IN MULTI-CORE SYSTEM ([[US Patent Application 18449036. RESOURCE AVAILABILITY MANAGEMENT USING REAL-TIME TASK MANAGER IN MULTI-CORE SYSTEM simplified abstract|18449036]])=== | + | ===RESOURCE AVAILABILITY MANAGEMENT USING REAL-TIME TASK MANAGER IN MULTI-CORE SYSTEM ([[US Patent Application 18449036. RESOURCE AVAILABILITY MANAGEMENT USING REAL-TIME TASK MANAGER IN MULTI-CORE SYSTEM simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|18449036]])=== |
Line 98: | Line 65: | ||
− | ===DATA PROCESSING PIPELINE ([[US Patent Application 18175333. DATA PROCESSING PIPELINE simplified abstract|18175333]])=== | + | ===DATA PROCESSING PIPELINE ([[US Patent Application 18175333. DATA PROCESSING PIPELINE simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|18175333]])=== |
Line 106: | Line 73: | ||
− | ===FFT ENGINE HAVING COMBINED BIT-REVERSAL AND MEMORY TRANSPOSE OPERATIONS ([[US Patent Application 18447029. FFT ENGINE HAVING COMBINED BIT-REVERSAL AND MEMORY TRANSPOSE OPERATIONS simplified abstract|18447029]])=== | + | ===FFT ENGINE HAVING COMBINED BIT-REVERSAL AND MEMORY TRANSPOSE OPERATIONS ([[US Patent Application 18447029. FFT ENGINE HAVING COMBINED BIT-REVERSAL AND MEMORY TRANSPOSE OPERATIONS simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|18447029]])=== |
Line 114: | Line 81: | ||
− | ===THEFT DETECTOR ([[US Patent Application 18326176. THEFT DETECTOR simplified abstract|18326176]])=== | + | ===THEFT DETECTOR ([[US Patent Application 18326176. THEFT DETECTOR simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|18326176]])=== |
Line 122: | Line 89: | ||
− | ===TRANSFORMER WITH BOTTOM COIL SHIELDING FOR IMPROVED EMI AND THERMAL CHARACTERISTICS ([[US Patent Application 17829073. TRANSFORMER WITH BOTTOM COIL SHIELDING FOR IMPROVED EMI AND THERMAL CHARACTERISTICS simplified abstract|17829073]])=== | + | ===TRANSFORMER WITH BOTTOM COIL SHIELDING FOR IMPROVED EMI AND THERMAL CHARACTERISTICS ([[US Patent Application 17829073. TRANSFORMER WITH BOTTOM COIL SHIELDING FOR IMPROVED EMI AND THERMAL CHARACTERISTICS simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|17829073]])=== |
Line 130: | Line 97: | ||
− | ===DIELECTRIC SILICON NITRIDE BARRIER DEPOSITION PROCESS FOR IMPROVED METAL LEAKAGE AND ADHESION ([[US Patent Application 17751976. DIELECTRIC SILICON NITRIDE BARRIER DEPOSITION PROCESS FOR IMPROVED METAL LEAKAGE AND ADHESION simplified abstract|17751976]])=== | + | ===DIELECTRIC SILICON NITRIDE BARRIER DEPOSITION PROCESS FOR IMPROVED METAL LEAKAGE AND ADHESION ([[US Patent Application 17751976. DIELECTRIC SILICON NITRIDE BARRIER DEPOSITION PROCESS FOR IMPROVED METAL LEAKAGE AND ADHESION simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|17751976]])=== |
Line 138: | Line 105: | ||
− | ===REDUCING CROSS-WAFER VARIABILITY FOR MINIMUM WIDTH RESISTORS ([[US Patent Application 18446176. REDUCING CROSS-WAFER VARIABILITY FOR MINIMUM WIDTH RESISTORS simplified abstract|18446176]])=== | + | ===REDUCING CROSS-WAFER VARIABILITY FOR MINIMUM WIDTH RESISTORS ([[US Patent Application 18446176. REDUCING CROSS-WAFER VARIABILITY FOR MINIMUM WIDTH RESISTORS simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|18446176]])=== |
Line 146: | Line 113: | ||
− | ===POWER CONVERTER MODULE ([[US Patent Application 17828803. POWER CONVERTER MODULE simplified abstract|17828803]])=== | + | ===POWER CONVERTER MODULE ([[US Patent Application 17828803. POWER CONVERTER MODULE simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|17828803]])=== |
Line 154: | Line 121: | ||
− | ===DIE ATTACH FILM DIE PAD ISOLATION FOR SEMICONDUCTOR DEVICES ([[US Patent Application 17828947. DIE ATTACH FILM DIE PAD ISOLATION FOR SEMICONDUCTOR DEVICES simplified abstract|17828947]])=== | + | ===DIE ATTACH FILM DIE PAD ISOLATION FOR SEMICONDUCTOR DEVICES ([[US Patent Application 17828947. DIE ATTACH FILM DIE PAD ISOLATION FOR SEMICONDUCTOR DEVICES simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|17828947]])=== |
Line 162: | Line 129: | ||
− | ===LASER ABLATION FOR DIE SEPARATION TO REDUCE LASER SPLASH AND ELECTRONIC DEVICE ([[US Patent Application 17826764. LASER ABLATION FOR DIE SEPARATION TO REDUCE LASER SPLASH AND ELECTRONIC DEVICE simplified abstract|17826764]])=== | + | ===LASER ABLATION FOR DIE SEPARATION TO REDUCE LASER SPLASH AND ELECTRONIC DEVICE ([[US Patent Application 17826764. LASER ABLATION FOR DIE SEPARATION TO REDUCE LASER SPLASH AND ELECTRONIC DEVICE simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|17826764]])=== |
Line 170: | Line 137: | ||
− | ===INTEGRATED MAGNETIC ASSEMBLY WITH CONDUCTIVE FIELD PLATES ([[US Patent Application 18450291. INTEGRATED MAGNETIC ASSEMBLY WITH CONDUCTIVE FIELD PLATES simplified abstract|18450291]])=== | + | ===INTEGRATED MAGNETIC ASSEMBLY WITH CONDUCTIVE FIELD PLATES ([[US Patent Application 18450291. INTEGRATED MAGNETIC ASSEMBLY WITH CONDUCTIVE FIELD PLATES simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|18450291]])=== |
Line 178: | Line 145: | ||
− | ===SELECTIVE EPITAXY TO CREATE A DOUBLE-DIFFUSED CHANNEL OVER PLANAR OR UNDERLYING TOPOGRAPHY ([[US Patent Application 17826872. SELECTIVE EPITAXY TO CREATE A DOUBLE-DIFFUSED CHANNEL OVER PLANAR OR UNDERLYING TOPOGRAPHY simplified abstract|17826872]])=== | + | ===SELECTIVE EPITAXY TO CREATE A DOUBLE-DIFFUSED CHANNEL OVER PLANAR OR UNDERLYING TOPOGRAPHY ([[US Patent Application 17826872. SELECTIVE EPITAXY TO CREATE A DOUBLE-DIFFUSED CHANNEL OVER PLANAR OR UNDERLYING TOPOGRAPHY simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|17826872]])=== |
Line 186: | Line 153: | ||
− | ===SYSTEM AND METHOD FOR ESTIMATING A CURRENT IN AN INDUCTOR OF A POWER CONVERTER ([[US Patent Application 17829090. SYSTEM AND METHOD FOR ESTIMATING A CURRENT IN AN INDUCTOR OF A POWER CONVERTER simplified abstract|17829090]])=== | + | ===SYSTEM AND METHOD FOR ESTIMATING A CURRENT IN AN INDUCTOR OF A POWER CONVERTER ([[US Patent Application 17829090. SYSTEM AND METHOD FOR ESTIMATING A CURRENT IN AN INDUCTOR OF A POWER CONVERTER simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|17829090]])=== |
Line 194: | Line 161: | ||
− | ===ADAPTIVE ON-TIME FOR VOLTAGE CONVERTER ([[US Patent Application 17829035. ADAPTIVE ON-TIME FOR VOLTAGE CONVERTER simplified abstract|17829035]])=== | + | ===ADAPTIVE ON-TIME FOR VOLTAGE CONVERTER ([[US Patent Application 17829035. ADAPTIVE ON-TIME FOR VOLTAGE CONVERTER simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|17829035]])=== |
Line 202: | Line 169: | ||
− | ===PRE-BIASED DUAL CURRENT SENSING ([[US Patent Application 17827406. PRE-BIASED DUAL CURRENT SENSING simplified abstract|17827406]])=== | + | ===PRE-BIASED DUAL CURRENT SENSING ([[US Patent Application 17827406. PRE-BIASED DUAL CURRENT SENSING simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|17827406]])=== |
Line 210: | Line 177: | ||
− | ===FLOATING HIGH-VOLTAGE LEVEL TRANSLATOR WITH ADAPTIVE BYPASS CIRCUIT ([[US Patent Application 17828797. FLOATING HIGH-VOLTAGE LEVEL TRANSLATOR WITH ADAPTIVE BYPASS CIRCUIT simplified abstract|17828797]])=== | + | ===FLOATING HIGH-VOLTAGE LEVEL TRANSLATOR WITH ADAPTIVE BYPASS CIRCUIT ([[US Patent Application 17828797. FLOATING HIGH-VOLTAGE LEVEL TRANSLATOR WITH ADAPTIVE BYPASS CIRCUIT simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|17828797]])=== |
Line 218: | Line 185: | ||
− | ===ADJUSTABLE PHASE LOCKED LOOP ([[US Patent Application 18448319. ADJUSTABLE PHASE LOCKED LOOP simplified abstract|18448319]])=== | + | ===ADJUSTABLE PHASE LOCKED LOOP ([[US Patent Application 18448319. ADJUSTABLE PHASE LOCKED LOOP simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|18448319]])=== |
Line 226: | Line 193: | ||
− | ===ANALOG-TO-DIGITAL CONVERTER (ADC) HAVING LINEARIZATION CIRCUIT WITH RECONFIGURABLE LOOKUP TABLE (LUT) MEMORY AND CALIBRATION OPTIONS ([[US Patent Application 17825864. ANALOG-TO-DIGITAL CONVERTER (ADC) HAVING LINEARIZATION CIRCUIT WITH RECONFIGURABLE LOOKUP TABLE (LUT) MEMORY AND CALIBRATION OPTIONS simplified abstract|17825864]])=== | + | ===ANALOG-TO-DIGITAL CONVERTER (ADC) HAVING LINEARIZATION CIRCUIT WITH RECONFIGURABLE LOOKUP TABLE (LUT) MEMORY AND CALIBRATION OPTIONS ([[US Patent Application 17825864. ANALOG-TO-DIGITAL CONVERTER (ADC) HAVING LINEARIZATION CIRCUIT WITH RECONFIGURABLE LOOKUP TABLE (LUT) MEMORY AND CALIBRATION OPTIONS simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|17825864]])=== |
Line 234: | Line 201: | ||
− | ===ANALOG-TO-DIGITAL CONVERTER (ADC) HAVING SELECTIVE COMPARATOR OFFSET ERROR TRACKING AND RELATED CORRECTIONS ([[US Patent Application 17828967. ANALOG-TO-DIGITAL CONVERTER (ADC) HAVING SELECTIVE COMPARATOR OFFSET ERROR TRACKING AND RELATED CORRECTIONS simplified abstract|17828967]])=== | + | ===ANALOG-TO-DIGITAL CONVERTER (ADC) HAVING SELECTIVE COMPARATOR OFFSET ERROR TRACKING AND RELATED CORRECTIONS ([[US Patent Application 17828967. ANALOG-TO-DIGITAL CONVERTER (ADC) HAVING SELECTIVE COMPARATOR OFFSET ERROR TRACKING AND RELATED CORRECTIONS simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|17828967]])=== |
Line 242: | Line 209: | ||
− | ===ESTIMATION AND PRE-COMPENSATION OF HARMONIC COUPLING SPURS ([[US Patent Application 17829218. ESTIMATION AND PRE-COMPENSATION OF HARMONIC COUPLING SPURS simplified abstract|17829218]])=== | + | ===ESTIMATION AND PRE-COMPENSATION OF HARMONIC COUPLING SPURS ([[US Patent Application 17829218. ESTIMATION AND PRE-COMPENSATION OF HARMONIC COUPLING SPURS simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|17829218]])=== |
Line 250: | Line 217: | ||
− | ===DIGITAL DISPLAY SYSTEM AND METHOD ([[US Patent Application 18448205. DIGITAL DISPLAY SYSTEM AND METHOD simplified abstract|18448205]])=== | + | ===DIGITAL DISPLAY SYSTEM AND METHOD ([[US Patent Application 18448205. DIGITAL DISPLAY SYSTEM AND METHOD simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|18448205]])=== |
Line 258: | Line 225: | ||
− | ===INTEGRATED CIRCUIT WITH MULTI-APPLICATION IMAGE PROCESSING ([[US Patent Application 18194249. INTEGRATED CIRCUIT WITH MULTI-APPLICATION IMAGE PROCESSING simplified abstract|18194249]])=== | + | ===INTEGRATED CIRCUIT WITH MULTI-APPLICATION IMAGE PROCESSING ([[US Patent Application 18194249. INTEGRATED CIRCUIT WITH MULTI-APPLICATION IMAGE PROCESSING simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|18194249]])=== |
Line 266: | Line 233: | ||
− | ===WIRELESS MANAGEMENT OF MODULAR SUBSYSTEMS WITH PROXY NODE OPTIONS ([[US Patent Application 18232451. WIRELESS MANAGEMENT OF MODULAR SUBSYSTEMS WITH PROXY NODE OPTIONS simplified abstract|18232451]])=== | + | ===WIRELESS MANAGEMENT OF MODULAR SUBSYSTEMS WITH PROXY NODE OPTIONS ([[US Patent Application 18232451. WIRELESS MANAGEMENT OF MODULAR SUBSYSTEMS WITH PROXY NODE OPTIONS simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|18232451]])=== |
Line 274: | Line 241: | ||
− | ===EFFICIENT UNICAST SUPER FRAME COMMUNICATIONS ([[US Patent Application 17828895. EFFICIENT UNICAST SUPER FRAME COMMUNICATIONS simplified abstract|17828895]])=== | + | ===EFFICIENT UNICAST SUPER FRAME COMMUNICATIONS ([[US Patent Application 17828895. EFFICIENT UNICAST SUPER FRAME COMMUNICATIONS simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|17828895]])=== |
Line 282: | Line 249: | ||
− | ===FREQUENCY CHANGE DURING CONNECTION EVENT ([[US Patent Application 17828225. FREQUENCY CHANGE DURING CONNECTION EVENT simplified abstract|17828225]])=== | + | ===FREQUENCY CHANGE DURING CONNECTION EVENT ([[US Patent Application 17828225. FREQUENCY CHANGE DURING CONNECTION EVENT simplified abstract (TEXAS INSTRUMENTS INCORPORATED)|17828225]])=== |
Revision as of 07:03, 5 December 2023
Contents
- 1 Patent applications for TEXAS INSTRUMENTS INCORPORATED on November 30th, 2023
- 1.1 QUICK TURN OFF OF CONTACTOR SYSTEM DURING POWER OFF (17826822)
- 1.2 SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS (18234003)
- 1.3 FSM BASED CLOCK SWITCHING OF ASYNCHRONOUS CLOCKS (17824695)
- 1.4 STATIC POWER REDUCTION IN CACHES USING DETERMINISTIC NAPS (18450079)
- 1.5 CONFIGURABLE CACHE FOR COHERENT SYSTEM (18229814)
- 1.6 STREAMING ENGINE WITH EARLY EXIT FROM LOOP LEVELS SUPPORTING EARLY EXIT LOOPS AND IRREGULAR LOOPS (18361985)
- 1.7 HARDWARE EVENT TRIGGERED PIPELINE CONTROL (18175364)
- 1.8 RESOURCE AVAILABILITY MANAGEMENT USING REAL-TIME TASK MANAGER IN MULTI-CORE SYSTEM (18449036)
- 1.9 DATA PROCESSING PIPELINE (18175333)
- 1.10 FFT ENGINE HAVING COMBINED BIT-REVERSAL AND MEMORY TRANSPOSE OPERATIONS (18447029)
- 1.11 THEFT DETECTOR (18326176)
- 1.12 TRANSFORMER WITH BOTTOM COIL SHIELDING FOR IMPROVED EMI AND THERMAL CHARACTERISTICS (17829073)
- 1.13 DIELECTRIC SILICON NITRIDE BARRIER DEPOSITION PROCESS FOR IMPROVED METAL LEAKAGE AND ADHESION (17751976)
- 1.14 REDUCING CROSS-WAFER VARIABILITY FOR MINIMUM WIDTH RESISTORS (18446176)
- 1.15 POWER CONVERTER MODULE (17828803)
- 1.16 DIE ATTACH FILM DIE PAD ISOLATION FOR SEMICONDUCTOR DEVICES (17828947)
- 1.17 LASER ABLATION FOR DIE SEPARATION TO REDUCE LASER SPLASH AND ELECTRONIC DEVICE (17826764)
- 1.18 INTEGRATED MAGNETIC ASSEMBLY WITH CONDUCTIVE FIELD PLATES (18450291)
- 1.19 SELECTIVE EPITAXY TO CREATE A DOUBLE-DIFFUSED CHANNEL OVER PLANAR OR UNDERLYING TOPOGRAPHY (17826872)
- 1.20 SYSTEM AND METHOD FOR ESTIMATING A CURRENT IN AN INDUCTOR OF A POWER CONVERTER (17829090)
- 1.21 ADAPTIVE ON-TIME FOR VOLTAGE CONVERTER (17829035)
- 1.22 PRE-BIASED DUAL CURRENT SENSING (17827406)
- 1.23 FLOATING HIGH-VOLTAGE LEVEL TRANSLATOR WITH ADAPTIVE BYPASS CIRCUIT (17828797)
- 1.24 ADJUSTABLE PHASE LOCKED LOOP (18448319)
- 1.25 ANALOG-TO-DIGITAL CONVERTER (ADC) HAVING LINEARIZATION CIRCUIT WITH RECONFIGURABLE LOOKUP TABLE (LUT) MEMORY AND CALIBRATION OPTIONS (17825864)
- 1.26 ANALOG-TO-DIGITAL CONVERTER (ADC) HAVING SELECTIVE COMPARATOR OFFSET ERROR TRACKING AND RELATED CORRECTIONS (17828967)
- 1.27 ESTIMATION AND PRE-COMPENSATION OF HARMONIC COUPLING SPURS (17829218)
- 1.28 DIGITAL DISPLAY SYSTEM AND METHOD (18448205)
- 1.29 INTEGRATED CIRCUIT WITH MULTI-APPLICATION IMAGE PROCESSING (18194249)
- 1.30 WIRELESS MANAGEMENT OF MODULAR SUBSYSTEMS WITH PROXY NODE OPTIONS (18232451)
- 1.31 EFFICIENT UNICAST SUPER FRAME COMMUNICATIONS (17828895)
- 1.32 FREQUENCY CHANGE DURING CONNECTION EVENT (17828225)
Patent applications for TEXAS INSTRUMENTS INCORPORATED on November 30th, 2023
QUICK TURN OFF OF CONTACTOR SYSTEM DURING POWER OFF (17826822)
Main Inventor
Priyank Anand
SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS (18234003)
Main Inventor
Lee D. Whetsel
FSM BASED CLOCK SWITCHING OF ASYNCHRONOUS CLOCKS (17824695)
Main Inventor
Atul Ramakant LELE
STATIC POWER REDUCTION IN CACHES USING DETERMINISTIC NAPS (18450079)
Main Inventor
Oluleye Olorode
CONFIGURABLE CACHE FOR COHERENT SYSTEM (18229814)
Main Inventor
Kai CHIRCA
STREAMING ENGINE WITH EARLY EXIT FROM LOOP LEVELS SUPPORTING EARLY EXIT LOOPS AND IRREGULAR LOOPS (18361985)
Main Inventor
Joseph Zbiciak
HARDWARE EVENT TRIGGERED PIPELINE CONTROL (18175364)
Main Inventor
Niraj Nandan
RESOURCE AVAILABILITY MANAGEMENT USING REAL-TIME TASK MANAGER IN MULTI-CORE SYSTEM (18449036)
Main Inventor
Anjandeep Singh SAHNI
DATA PROCESSING PIPELINE (18175333)
Main Inventor
Mihir Mody
FFT ENGINE HAVING COMBINED BIT-REVERSAL AND MEMORY TRANSPOSE OPERATIONS (18447029)
Main Inventor
Indu PRATHAPAN
THEFT DETECTOR (18326176)
Main Inventor
Veeramanikandan RAJU
TRANSFORMER WITH BOTTOM COIL SHIELDING FOR IMPROVED EMI AND THERMAL CHARACTERISTICS (17829073)
Main Inventor
Nicola BERTONI
DIELECTRIC SILICON NITRIDE BARRIER DEPOSITION PROCESS FOR IMPROVED METAL LEAKAGE AND ADHESION (17751976)
Main Inventor
Qi-Zhong Hong
REDUCING CROSS-WAFER VARIABILITY FOR MINIMUM WIDTH RESISTORS (18446176)
Main Inventor
Mahalingam Nandakumar
POWER CONVERTER MODULE (17828803)
Main Inventor
WOOCHAN KIM
DIE ATTACH FILM DIE PAD ISOLATION FOR SEMICONDUCTOR DEVICES (17828947)
Main Inventor
Jesus Bajo Bautista
LASER ABLATION FOR DIE SEPARATION TO REDUCE LASER SPLASH AND ELECTRONIC DEVICE (17826764)
Main Inventor
Michael Todd Wyant
INTEGRATED MAGNETIC ASSEMBLY WITH CONDUCTIVE FIELD PLATES (18450291)
Main Inventor
Enis Tuncer
SELECTIVE EPITAXY TO CREATE A DOUBLE-DIFFUSED CHANNEL OVER PLANAR OR UNDERLYING TOPOGRAPHY (17826872)
Main Inventor
Sheldon Douglas HAYNIE
SYSTEM AND METHOD FOR ESTIMATING A CURRENT IN AN INDUCTOR OF A POWER CONVERTER (17829090)
Main Inventor
Isaac Cohen
ADAPTIVE ON-TIME FOR VOLTAGE CONVERTER (17829035)
Main Inventor
Sombuddha CHAKRABORTY
PRE-BIASED DUAL CURRENT SENSING (17827406)
Main Inventor
Venkatesh GUDURI
FLOATING HIGH-VOLTAGE LEVEL TRANSLATOR WITH ADAPTIVE BYPASS CIRCUIT (17828797)
Main Inventor
Tuli Luthuli Dake
ADJUSTABLE PHASE LOCKED LOOP (18448319)
Main Inventor
Florian Neveu
ANALOG-TO-DIGITAL CONVERTER (ADC) HAVING LINEARIZATION CIRCUIT WITH RECONFIGURABLE LOOKUP TABLE (LUT) MEMORY AND CALIBRATION OPTIONS (17825864)
Main Inventor
Narasimhan RAJAGOPAL
ANALOG-TO-DIGITAL CONVERTER (ADC) HAVING SELECTIVE COMPARATOR OFFSET ERROR TRACKING AND RELATED CORRECTIONS (17828967)
Main Inventor
Viswanathan NAGARAJAN
ESTIMATION AND PRE-COMPENSATION OF HARMONIC COUPLING SPURS (17829218)
Main Inventor
Sarma Sundareswara GUNTURI
DIGITAL DISPLAY SYSTEM AND METHOD (18448205)
Main Inventor
Kristofer Scott OBERASCHER
INTEGRATED CIRCUIT WITH MULTI-APPLICATION IMAGE PROCESSING (18194249)
Main Inventor
Niraj Nandan
WIRELESS MANAGEMENT OF MODULAR SUBSYSTEMS WITH PROXY NODE OPTIONS (18232451)
Main Inventor
Ariton E. XHAFA
EFFICIENT UNICAST SUPER FRAME COMMUNICATIONS (17828895)
Main Inventor
Ariton E. XHAFA
FREQUENCY CHANGE DURING CONNECTION EVENT (17828225)
Main Inventor
Yaron Alpert