Difference between revisions of "TEST ARCHITECTURE FOR 3D STACKED CIRCUITS: abstract simplified (17700329)"

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In this abstract, the concept of stacked circuits is introduced. Stacked circuits are designed to make testing after stacking easier. The abstract describes an example of a stacked circuit that consists of two dies connected through multiple interconnects. The first die has various components, including a test input interface to receive test data signals and a source test clock signal, a test output interface to transmit test responses, a first test signal path, and interfaces to communicate with the second die. These interfaces allow the transmission of test data signals and a low-latency clock signal between the two dies. The second die also has interfaces to receive test responses and the clock signal from the first die. The abstract concludes by mentioning that there are other aspects, embodiments, and features included in stacked circuits.
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The abstract describes a configuration of stacked circuits that allows for easier testing after the circuits have been stacked together. In this configuration, two circuits, referred to as "dies," are connected through multiple interconnects. The first die has interfaces for receiving test data signals and a clock signal, as well as interfaces for conveying test responses. It also has pathways for transmitting test signals and a low-latency clock signal to the second die, and interfaces for receiving test responses and the clock signal from the second die. The abstract mentions that there are other aspects and features included, but does not provide specific details.

Latest revision as of 16:20, 1 October 2023

The abstract describes a configuration of stacked circuits that allows for easier testing after the circuits have been stacked together. In this configuration, two circuits, referred to as "dies," are connected through multiple interconnects. The first die has interfaces for receiving test data signals and a clock signal, as well as interfaces for conveying test responses. It also has pathways for transmitting test signals and a low-latency clock signal to the second die, and interfaces for receiving test responses and the clock signal from the second die. The abstract mentions that there are other aspects and features included, but does not provide specific details.

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