Difference between revisions of "TEST ARCHITECTURE FOR 3D STACKED CIRCUITS: abstract simplified (17700329)"
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| − | The abstract describes a configuration of stacked circuits that | + | The abstract describes a configuration of stacked circuits that allows for easier testing after the circuits have been stacked together. In this configuration, two circuits, referred to as "dies," are connected through multiple interconnects. The first die has interfaces for receiving test data signals and a clock signal, as well as interfaces for conveying test responses. It also has pathways for transmitting test signals and a low-latency clock signal to the second die, and interfaces for receiving test responses and the clock signal from the second die. The abstract mentions that there are other aspects and features included, but does not provide specific details. |
Latest revision as of 16:20, 1 October 2023
The abstract describes a configuration of stacked circuits that allows for easier testing after the circuits have been stacked together. In this configuration, two circuits, referred to as "dies," are connected through multiple interconnects. The first die has interfaces for receiving test data signals and a clock signal, as well as interfaces for conveying test responses. It also has pathways for transmitting test signals and a low-latency clock signal to the second die, and interfaces for receiving test responses and the clock signal from the second die. The abstract mentions that there are other aspects and features included, but does not provide specific details.
