Difference between revisions of "SanDisk Technologies LLC patent applications published on November 30th, 2023"

From WikiPatents
Jump to navigation Jump to search
 
(15 intermediate revisions by the same user not shown)
Line 26: Line 26:
 
==Patent applications for SanDisk Technologies LLC on November 30th, 2023==
 
==Patent applications for SanDisk Technologies LLC on November 30th, 2023==
  
−
===CHIP SELECT, COMMAND, AND ADDRESS ENCODING ([[US Patent Application 17828921. CHIP SELECT, COMMAND, AND ADDRESS ENCODING simplified abstract|17828921]])===
+
===CHIP SELECT, COMMAND, AND ADDRESS ENCODING ([[US Patent Application 17828921. CHIP SELECT, COMMAND, AND ADDRESS ENCODING simplified abstract (SanDisk Technologies LLC)|17828921]])===
  
  
Line 34: Line 34:
  
  
−
'''Brief explanation'''
+
===CROSS-POINT ARRAY REFRESH SCHEME ([[US Patent Application 17824806. CROSS-POINT ARRAY REFRESH SCHEME simplified abstract (SanDisk Technologies LLC)|17824806]])===
−
The patent application describes a new way to perform command/address sequences for memory devices without using the I/O bus, improving performance.
 
−
* The command/address sequence can be done in parallel with DIN/DOUT operations, eliminating a performance bottleneck.
 
−
* Bit information is encoded on enable signals and latched using rising or falling edges of a clock signal.
 
−
* The encoded bit information is decoded to determine command and address codes.
 
−
* A chip select sequence is also disclosed, allowing multiple memory chips to share a common connection without needing hard-coded pins for chip select.
 
−
 
 
−
'''Abstract'''
 
−
A command/address sequence associated with a read/write operation for a memory device utilizes various existing command/address clock signals in a novel way that obviates the need to utilize the I/O bus. As such, the command/address sequence can be performed in parallel with the DIN/DOUT operations, thereby removing the performance bottleneck that would otherwise be caused by the command and address sequencing. The command/address sequence encodes bit information on first and second enable signals and utilizes rising or falling edges of a clock signal to latch the encoded bit information, which can then be decoded to determine corresponding command and address codes. A chip select sequence is also disclosed that enables a memory chip configuration to be employed in which each chip in a package shares a common connection to a controller but does not require hard-coded pins for performing chip select.
 
−
 
 
−
===CROSS-POINT ARRAY REFRESH SCHEME ([[US Patent Application 17824806. CROSS-POINT ARRAY REFRESH SCHEME simplified abstract|17824806]])===
 
  
  
Line 52: Line 42:
  
  
−
'''Brief explanation'''
+
===HIGH SPEED MULTI-LEVEL CELL (MLC) PROGRAMMING IN NON-VOLATILE MEMORY STRUCTURES ([[US Patent Application 17825048. HIGH SPEED MULTI-LEVEL CELL (MLC) PROGRAMMING IN NON-VOLATILE MEMORY STRUCTURES simplified abstract (SanDisk Technologies LLC)|17825048]])===
−
- This patent application describes technology for refreshing threshold switching selectors in programmable resistance memory cells in cross-point memory arrays.
 
−
- The Vt (threshold voltage) of the threshold switching selector can change over time, which can affect the performance of the memory system.
 
−
- The memory system uses a selector refresh operation to reset the Vt of the threshold switching selectors and a separate data refresh operation to refresh data in the memory elements.
 
−
- The data refresh operation can also refresh the selector, but the selector refresh operation is faster.
 
−
- The selector refresh operation consumes less power and current compared to the data refresh operation.
 
−
- As a result, the selector refresh operation can be performed more frequently than the data refresh operation.
 
−
 
 
−
'''Abstract'''
 
−
Technology is disclosed herein for refreshing threshold switching selectors in programmable resistance memory cells in cross-point memory arrays. The Vt of the threshold switching selector may drift over time. The memory system resets the Vt of the threshold switching selectors with a selector refresh operation and uses a separate data refresh operation to refresh data in programmable resistance memory elements. The data refresh operation itself may also refresh the selector. However, the threshold switching selector refresh operation is faster than the data refresh operation. Moreover, the selector refresh operation consumes much less power and/or current then the data refresh operation. The selector refresh operation may thus be performed at a higher rate than the data refresh operation.
 
−
 
 
−
===HIGH SPEED MULTI-LEVEL CELL (MLC) PROGRAMMING IN NON-VOLATILE MEMORY STRUCTURES ([[US Patent Application 17825048. HIGH SPEED MULTI-LEVEL CELL (MLC) PROGRAMMING IN NON-VOLATILE MEMORY STRUCTURES simplified abstract|17825048]])===
 
  
  
Line 71: Line 50:
  
  
−
'''Brief explanation'''
+
===LOW POWER MULTI-LEVEL CELL (MLC) PROGRAMMING IN NON-VOLATILE MEMORY STRUCTURES ([[US Patent Application 17825193. LOW POWER MULTI-LEVEL CELL (MLC) PROGRAMMING IN NON-VOLATILE MEMORY STRUCTURES simplified abstract (SanDisk Technologies LLC)|17825193]])===
−
The abstract describes a method for programming a memory array of a non-volatile memory structure, specifically MLC NAND-type memory cells. The method involves two program pulses to program selected memory cells.
 
−
 
 
−
* The method is for programming a memory array of a non-volatile memory structure.
 
−
* The memory array consists of MLC NAND-type memory cells.
 
−
* The method involves two program pulses.
 
−
* In the first program pulse, selected memory cells are programmed according to a first programmable state and a second programmable state.
 
−
* In the second program pulse, the selected memory cells are programmed according to a third programmable state.
 
−
 
 
−
'''Abstract'''
 
−
A method for programming a memory array of a non-volatile memory structure, wherein the memory array comprises a population of MLC NAND-type memory cells, and the method comprises: (1) in a first program pulse, programming selected memory cells according to a first programmable state and a second programmable state, and (2) in a second program pulse, programming the selected memory cells according to a third programmable state.
 
−
 
 
−
===LOW POWER MULTI-LEVEL CELL (MLC) PROGRAMMING IN NON-VOLATILE MEMORY STRUCTURES ([[US Patent Application 17825193. LOW POWER MULTI-LEVEL CELL (MLC) PROGRAMMING IN NON-VOLATILE MEMORY STRUCTURES simplified abstract|17825193]])===
 
  
  
Line 91: Line 58:
  
  
−
'''Brief explanation'''
+
===NON-VOLATILE MEMORY WITH INTER-DIE CONNECTION ([[US Patent Application 17825337. NON-VOLATILE MEMORY WITH INTER-DIE CONNECTION simplified abstract (SanDisk Technologies LLC)|17825337]])===
−
The abstract describes a method for programming a memory array of a non-volatile memory structure, specifically a population of MLC NAND-type memory cells. The method involves applying an inhibit condition and a zero voltage condition to the bit lines of the memory array.
 
−
 
 
−
* The method is used for programming a memory array of a non-volatile memory structure.
 
−
* The memory array consists of MLC NAND-type memory cells.
 
−
* The method involves applying an inhibit condition to one or more bit lines of the memory array.
 
−
* The method also involves applying a zero voltage condition to one or more bit lines of the memory array.
 
−
* The goal is to ensure that less than half of the adjacent bit lines of the memory array experience a voltage swing between the inhibit condition and the zero voltage condition.
 
−
 
 
−
'''Abstract'''
 
−
A method for programming a memory array of a non-volatile memory structure, the memory comprising a population of MLC NAND-type memory cells, wherein the method comprises applying: (1) an inhibit condition to one or more bit lines of the memory array, and (2) a zero voltage condition to one or more bit lines of the memory array such that less than half of the adjacent bit lines of the memory array experience a voltage swing between the inhibit condition and the zero voltage condition.
 
−
 
 
−
===NON-VOLATILE MEMORY WITH INTER-DIE CONNECTION ([[US Patent Application 17825337. NON-VOLATILE MEMORY WITH INTER-DIE CONNECTION simplified abstract|17825337]])===
 
  
  
Line 111: Line 66:
  
  
−
'''Brief explanation'''
+
===METHOD TO OPTIMIZE FIRST READ VERSUS SECOND READ MARGIN BY SWITCHING BOOST TIMING ([[US Patent Application 17824350. METHOD TO OPTIMIZE FIRST READ VERSUS SECOND READ MARGIN BY SWITCHING BOOST TIMING simplified abstract (SanDisk Technologies LLC)|17824350]])===
−
The patent application describes a non-volatile memory apparatus that consists of a stack of integrated memory assemblies.
 
−
* Each integrated memory assembly includes a memory die and a control die, which are connected by a set of power pads and metal lines.
 
−
* The memory dies have a non-volatile memory structure and a top metal layer for transmitting power signals.
 
−
* The control dies have a control circuit for performing memory operations and a set of metal layers.
 
−
* The substrate of the control dies has conductive vias that connect to the top metal layer of the memory die in the adjacent assembly, allowing signals to be routed between the integrated memory assemblies.
 
−
 
 
−
'''Abstract'''
 
−
A non-volatile memory apparatus comprises a stack of integrated memory assemblies. Each integrated memory assembly includes a memory die bonded to a control die and a set of power pads connected to metal lines in the respective memory die and control die. The memory dies comprise a non-volatile memory structure and a top metal layer for transmitting power signals above the memory structure. The control dies comprise a substrate, a control circuit positioned on the substrate for performing memory operations on a corresponding memory structure and a set of metals layers above the control circuit. The substrate comprises a set of conductive vias through the substrate that connect at one end to the top metal layer of the memory die of an adjacent integrated memory assembly and connect at a second end to the set of metals layers above the control circuit for routing signals between integrated memory assemblies.
 
−
 
 
−
===METHOD TO OPTIMIZE FIRST READ VERSUS SECOND READ MARGIN BY SWITCHING BOOST TIMING ([[US Patent Application 17824350. METHOD TO OPTIMIZE FIRST READ VERSUS SECOND READ MARGIN BY SWITCHING BOOST TIMING simplified abstract|17824350]])===
 
  
  
Line 129: Line 74:
  
  
−
'''Brief explanation'''
+
===SYSTEMS AND METHODS OF CORRECTING ERRORS IN UNMATCHED MEMORY DEVICES ([[US Patent Application 17827562. SYSTEMS AND METHODS OF CORRECTING ERRORS IN UNMATCHED MEMORY DEVICES simplified abstract (SanDisk Technologies LLC)|17827562]])===
−
The patent application describes an apparatus with multiple memory cells and a control circuit.
 
−
* The control circuit is responsible for performing a read operation on the memory cells.
 
−
* During the read operation, the control circuit determines the read condition of a memory cell.
 
−
* The read condition can be one of several possible conditions.
 
−
* The control circuit also determines the boost timing for the memory cell based on its read condition.
 
−
* The boost timing is a specific timing that corresponds to the read condition of the memory cell.
 
−
 
 
−
'''Abstract'''
 
−
An apparatus that comprises a plurality of memory cells and a control circuit coupled to the plurality of memory cells is disclosed. The control circuit is configured to perform a read operation. The read operation includes determining a read condition of a memory cell, where the read condition is of a plurality of read conditions and determining a boost timing for the memory cell, where the boost timing corresponds to the read condition.
 
−
 
 
−
===SYSTEMS AND METHODS OF CORRECTING ERRORS IN UNMATCHED MEMORY DEVICES ([[US Patent Application 17827562. SYSTEMS AND METHODS OF CORRECTING ERRORS IN UNMATCHED MEMORY DEVICES simplified abstract|17827562]])===
 
  
  
Line 148: Line 82:
  
  
−
'''Brief explanation'''
+
===NON-VOLATILE MEMORY WITH ENGINEERED CHANNEL GRADIENT ([[US Patent Application 17828685. NON-VOLATILE MEMORY WITH ENGINEERED CHANNEL GRADIENT simplified abstract (SanDisk Technologies LLC)|17828685]])===
−
- The patent application describes systems and methods for correcting errors in unmatched memory devices.
 
−
- The embodiments train a memory interface to determine a duty cycle timing for a clock signal in a data window formed by a data signal in a memory cell.
 
−
- The duty cycle timing identifies an initial trained timing in the data window where the setup portion and hold portion of the data window are approximately equal in length.
 
−
- An event is identified that shifts the duty cycle timing away from the initial trained timing.
 
−
- A retraining of the memory interface is triggered based on a determination that at least one of two points defined about the initial trained timing fails a two-point sampling.
 
−
 
 
−
'''Abstract'''
 
−
Systems and methods are provided for correcting errors in unmatched memory devices. Various embodiments herein train a memory interface to determine a duty cycle timing for a clock signal in a data window formed by a data signal in a memory cell. The duty cycle timing identifies an initial trained timing in the data window at which a setup portion and a hold portion of the data window are approximately equal in length when the trigger signal is received at the initial trained timing. The embodiments herein also identify an event that shifts the duty cycle timing away from the initial trained timing, and triggers a retraining of the memory interface based on a determination that at least one of two points defined about the initial trained timing fails a two-point sampling.
 
−
 
 
−
===NON-VOLATILE MEMORY WITH ENGINEERED CHANNEL GRADIENT ([[US Patent Application 17828685. NON-VOLATILE MEMORY WITH ENGINEERED CHANNEL GRADIENT simplified abstract|17828685]])===
 
  
  
Line 166: Line 90:
  
  
−
'''Brief explanation'''
+
===TEMPERATURE DEPENDENT PROGRAMMING TECHNIQUES IN A MEMORY DEVICE ([[US Patent Application 17826434. TEMPERATURE DEPENDENT PROGRAMMING TECHNIQUES IN A MEMORY DEVICE simplified abstract (SanDisk Technologies LLC)|17826434]])===
−
The patent application describes a method to save power during the read process in NAND memory.
 
−
* NAND strings in each sub-block of a block have independently controlled source side select lines and drain side select lines.
 
−
* Unselected sub-blocks have floating NAND strings, which do not draw current.
 
−
* To prevent read disturb in unselected sub-blocks, nearby unselected word lines are lowered to intermediate voltages while the selected word line is lowered.
 
−
* This creates a channel potential gradient in the floated NAND strings of unselected sub-blocks that avoids read disturb.
 
−
* The selected word line is then raised to the appropriate read compare voltage for sensing the selected memory cells.
 
−
 
 
−
'''Abstract'''
 
−
To save power during a read process, NAND strings of each sub-block of a block have independently controlled source side select lines connected to source side select gates and drain side select lines connected to drain side select gates so that NAND strings of unselected sub-blocks can float and not draw current. To prevent read disturb in NAND strings of unselected sub-blocks, after all word lines are raised to a pass gate voltage, unselected word lines nearby the selected word line are lowered to respective intermediate voltages while lowering the voltage on the selected word line in order to achieve a channel potential gradient in the floated NAND strings of the unselected sub-blocks that does not result in read disturb. Subsequently, the selected word line is raised to the appropriate read compare voltage so the selected memory cells can be sensed.
 
−
 
 
−
===TEMPERATURE DEPENDENT PROGRAMMING TECHNIQUES IN A MEMORY DEVICE ([[US Patent Application 17826434. TEMPERATURE DEPENDENT PROGRAMMING TECHNIQUES IN A MEMORY DEVICE simplified abstract|17826434]])===
 
  
  
Line 185: Line 98:
  
  
−
'''Brief explanation'''
+
===SYSTEMS AND METHODS OF REDUCING DETECTION ERROR AND DUTY ERROR IN MEMORY DEVICES ([[US Patent Application 17828708. SYSTEMS AND METHODS OF REDUCING DETECTION ERROR AND DUTY ERROR IN MEMORY DEVICES simplified abstract (SanDisk Technologies LLC)|17828708]])===
−
The patent application describes a memory device with multiple memory cells arranged in word lines.
 
−
* The memory device has a controller that communicates with the memory cells.
 
−
* During programming, the controller measures the temperature of the memory device.
 
−
* The controller then programs the memory cells of a selected word line in multiple program loops until programming is completed or until the maximum number of program loops is reached.
 
−
* The maximum number of program loops is determined based on the detected temperature.
 
−
 
 
−
'''Abstract'''
 
−
The memory device that includes a plurality of memory cells that are arranged in a plurality of word lines. A controller is in electrical communication with the plurality of memory cells. During programming, the controller detects a temperature of the memory device. The controller then programs the memory cells of a selected word line of the plurality of word lines in a plurality of program loops until programming is completed or until the plurality of program loops is greater than a maximum number of program loops. The maximum number of program loops is dependent on the temperature that is detected.
 
−
 
 
−
===SYSTEMS AND METHODS OF REDUCING DETECTION ERROR AND DUTY ERROR IN MEMORY DEVICES ([[US Patent Application 17828708. SYSTEMS AND METHODS OF REDUCING DETECTION ERROR AND DUTY ERROR IN MEMORY DEVICES simplified abstract|17828708]])===
 
  
  
Line 203: Line 106:
  
  
−
'''Brief explanation'''
+
===THREE-DIMENSIONAL MEMORY DEVICE CONTAINING DUAL-DEPTH DRAIN-SELECT-LEVEL ISOLATION STRUCTURES AND METHODS FOR FORMING THE SAME ([[US Patent Application 17804184. THREE-DIMENSIONAL MEMORY DEVICE CONTAINING DUAL-DEPTH DRAIN-SELECT-LEVEL ISOLATION STRUCTURES AND METHODS FOR FORMING THE SAME simplified abstract (SanDisk Technologies LLC)|17804184]])===
−
The patent application describes systems and methods for reducing detection and duty cycle errors in memory devices.
 
−
* The invention combines a write duty cycle adjuster with write training techniques.
 
−
* The write duty cycle adjuster adjusts the duty cycle of a clock signal that coordinates a data signal with a data operation on the memory device.
 
−
* This adjustment is based on an error in the duty cycle, helping to reduce errors in the memory device.
 
−
* The write training operations detect any skew between the data signal and the clock signal.
 
−
* If a skew is detected, the sampling transition of the duty cycle of the clock signal is adjusted to align with a valid data window of the data signal.
 
−
* This alignment helps to ensure accurate data transfer and reduce errors in the memory device.
 
−
 
 
−
'''Abstract'''
 
−
Systems and methods are provided that combine a write duty cycle adjuster with write training to reduce detection and duty cycle errors in memory devices. Various embodiments herein perform write duty cycle adjuster operations to adjust a duty cycle of a clock signal that coordinates a data signal with a data operation on the memory device based on an error in the duty cycle, and performs write training operations to detect a skew between the data signal and the clock signal and adjust a sampling transition of the duty cycle of the clock signal to align with a valid data window of the data signal.
 
−
 
 
−
===THREE-DIMENSIONAL MEMORY DEVICE CONTAINING DUAL-DEPTH DRAIN-SELECT-LEVEL ISOLATION STRUCTURES AND METHODS FOR FORMING THE SAME ([[US Patent Application 17804184. THREE-DIMENSIONAL MEMORY DEVICE CONTAINING DUAL-DEPTH DRAIN-SELECT-LEVEL ISOLATION STRUCTURES AND METHODS FOR FORMING THE SAME simplified abstract|17804184]])===
 
  
  
Line 221: Line 112:
  
 
Akihiro TOBIOKA
 
Akihiro TOBIOKA
−
 
−
 
−
'''Brief explanation'''
 
−
The patent application describes a three-dimensional memory device that consists of alternating layers of insulating and electrically conductive materials.
 
−
* The device has memory openings that extend vertically through the alternating layers.
 
−
* Within each memory opening, there are memory opening fill structures.
 
−
* Composite drain-select-level isolation structures divide each drain-select-level electrically conductive layer into multiple electrically conductive strips.
 
−
* Each drain-select-level isolation structure includes a first isolation material portion that extends vertically through each drain-select-level electrically conductive layer.
 
−
* Additionally, there are second isolation material portions that also extend vertically through each drain-select-level electrically conductive layer and a topmost dummy electrically conductive layer.
 
−
 
−
'''Abstract'''
 
−
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located within a respective one of the memory openings. Composite drain-select-level isolation structures divide each drain-select-level electrically conductive layer into a respective plurality of electrically conductive strips. Each drain-select-level isolation structure includes a respective first drain-select-level isolation material portion vertically extending through each drain-select-level electrically conductive layers and a respective set of second drain-select-level isolation material portions vertically extending through each of the drain-select-level electrically conductive layers and at least a topmost dummy electrically conductive layer that underlies the drain-select-level electrically conductive layers.
 

Latest revision as of 14:53, 6 December 2023

Summary of the patent applications from SanDisk Technologies LLC on November 30th, 2023

SanDisk Technologies LLC has recently filed several patents related to memory devices and techniques for improving their performance and efficiency. These patents cover a range of technologies including three-dimensional memory devices, error reduction methods, power-saving techniques, and memory array programming methods.

In terms of memory devices, SanDisk Technologies LLC has developed a three-dimensional memory device that consists of alternating layers of insulating and electrically conductive materials. This device has memory openings with memory opening fill structures, and composite drain-select-level isolation structures that divide each drain-select-level electrically conductive layer into multiple electrically conductive strips.

To reduce detection and duty cycle errors in memory devices, the organization has combined a write duty cycle adjuster with write training techniques. The write duty cycle adjuster adjusts the duty cycle of a clock signal based on an error in the duty cycle, while write training operations detect and adjust any skew between the data signal and the clock signal.

In terms of memory programming, SanDisk Technologies LLC has developed methods for programming memory cells based on temperature measurements. The memory device's controller measures the temperature and adjusts the number of program loops accordingly.

To save power during the read process in NAND memory, the organization has developed techniques that independently control source side select lines and drain side select lines in NAND strings. Unselected sub-blocks have floating NAND strings to prevent current draw, and nearby unselected word lines are lowered to intermediate voltages to avoid read disturb.

Notable applications:

  • Three-dimensional memory device with alternating layers of insulating and electrically conductive materials.
  • Error reduction methods combining write duty cycle adjuster and write training techniques.
  • Memory device with temperature-based programming methods.
  • Power-saving techniques in NAND memory read process.
  • Memory apparatus with control circuit for read operations and boost timing determination.
  • Non-volatile memory apparatus with integrated memory assemblies connected by power pads and metal lines.
  • Memory array programming methods for non-volatile memory structures.
  • Technology for refreshing threshold switching selectors in programmable resistance memory cells.



Patent applications for SanDisk Technologies LLC on November 30th, 2023

CHIP SELECT, COMMAND, AND ADDRESS ENCODING (17828921)

Main Inventor

TIANYU TANG


CROSS-POINT ARRAY REFRESH SCHEME (17824806)

Main Inventor

Michael Nicolas Albert Tran


HIGH SPEED MULTI-LEVEL CELL (MLC) PROGRAMMING IN NON-VOLATILE MEMORY STRUCTURES (17825048)

Main Inventor

Xiang Yang


LOW POWER MULTI-LEVEL CELL (MLC) PROGRAMMING IN NON-VOLATILE MEMORY STRUCTURES (17825193)

Main Inventor

Xiang Yang


NON-VOLATILE MEMORY WITH INTER-DIE CONNECTION (17825337)

Main Inventor

Shiqian Shao


METHOD TO OPTIMIZE FIRST READ VERSUS SECOND READ MARGIN BY SWITCHING BOOST TIMING (17824350)

Main Inventor

Peng Wang


SYSTEMS AND METHODS OF CORRECTING ERRORS IN UNMATCHED MEMORY DEVICES (17827562)

Main Inventor

Venkatesh Prasad RAMACHANDRA


NON-VOLATILE MEMORY WITH ENGINEERED CHANNEL GRADIENT (17828685)

Main Inventor

Jiacen Guo


TEMPERATURE DEPENDENT PROGRAMMING TECHNIQUES IN A MEMORY DEVICE (17826434)

Main Inventor

Sujjatul Islam


SYSTEMS AND METHODS OF REDUCING DETECTION ERROR AND DUTY ERROR IN MEMORY DEVICES (17828708)

Main Inventor

Jang Woo Lee


THREE-DIMENSIONAL MEMORY DEVICE CONTAINING DUAL-DEPTH DRAIN-SELECT-LEVEL ISOLATION STRUCTURES AND METHODS FOR FORMING THE SAME (17804184)

Main Inventor

Akihiro TOBIOKA

Retrieved from "http://wikipatents.org/index.php?title=SanDisk_Technologies_LLC_patent_applications_published_on_November_30th,_2023&oldid=15351"