SanDisk Technologies LLC patent applications published on November 30th, 2023

Summary of the patent applications from SanDisk Technologies LLC on November 30th, 2023

SanDisk Technologies LLC has recently filed several patents related to memory devices and techniques for improving their performance and efficiency. These patents cover a range of technologies including three-dimensional memory devices, error reduction methods, power-saving techniques, and memory array programming methods.

In terms of memory devices, SanDisk Technologies LLC has developed a three-dimensional memory device that consists of alternating layers of insulating and electrically conductive materials. This device has memory openings with memory opening fill structures, and composite drain-select-level isolation structures that divide each drain-select-level electrically conductive layer into multiple electrically conductive strips.

To reduce detection and duty cycle errors in memory devices, the organization has combined a write duty cycle adjuster with write training techniques. The write duty cycle adjuster adjusts the duty cycle of a clock signal based on an error in the duty cycle, while write training operations detect and adjust any skew between the data signal and the clock signal.

In terms of memory programming, SanDisk Technologies LLC has developed methods for programming memory cells based on temperature measurements. The memory device's controller measures the temperature and adjusts the number of program loops accordingly.

To save power during the read process in NAND memory, the organization has developed techniques that independently control source side select lines and drain side select lines in NAND strings. Unselected sub-blocks have floating NAND strings to prevent current draw, and nearby unselected word lines are lowered to intermediate voltages to avoid read disturb.

Notable applications:

• Three-dimensional memory device with alternating layers of insulating and electrically conductive materials.
• Error reduction methods combining write duty cycle adjuster and write training techniques.
• Memory device with temperature-based programming methods.
• Power-saving techniques in NAND memory read process.
• Memory apparatus with control circuit for read operations and boost timing determination.
• Non-volatile memory apparatus with integrated memory assemblies connected by power pads and metal lines.
• Memory array programming methods for non-volatile memory structures.
• Technology for refreshing threshold switching selectors in programmable resistance memory cells.