Samsung electronics co., ltd. (20240135980). INTEGRATED CIRCUIT MEMORY DEVICES HAVING EFFICIENT ROW HAMMER MANAGEMENT AND MEMORY SYSTEMS INCLUDING THE SAME simplified abstract

INTEGRATED CIRCUIT MEMORY DEVICES HAVING EFFICIENT ROW HAMMER MANAGEMENT AND MEMORY SYSTEMS INCLUDING THE SAME

Organization Name

samsung electronics co., ltd.

Inventor(s)

Myungkyu Lee of Suwon-si (KR)

Eunae Lee of Suwon-si (KR)

Sunghye Cho of Suwon-si (KR)

Kyomin Sohn of Suwon-si (KR)

Kijun Lee of Suwon-si (KR)

INTEGRATED CIRCUIT MEMORY DEVICES HAVING EFFICIENT ROW HAMMER MANAGEMENT AND MEMORY SYSTEMS INCLUDING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240135980 titled 'INTEGRATED CIRCUIT MEMORY DEVICES HAVING EFFICIENT ROW HAMMER MANAGEMENT AND MEMORY SYSTEMS INCLUDING THE SAME

Simplified Explanation

The semiconductor memory device described in the patent application includes a row hammer management circuit that selects candidate hammer addresses from access row addresses received from the memory controller and performs hammer refresh operations on victim memory cell rows adjacent to the selected row.

• The row hammer management circuit receives access row addresses from the memory controller and stores randomly selected row addresses in a hammer address queue for hammer refresh operations.
• The refresh control circuit performs hammer refresh operations on victim memory cell rows physically adjacent to the selected row address to prevent data corruption.

Potential Applications

This technology can be applied in various semiconductor memory devices such as DRAMs to prevent data corruption due to row hammer effects.

Problems Solved

This technology solves the problem of data corruption in memory cells caused by repeated accesses to the same row, known as the row hammer effect.

Benefits

The benefits of this technology include improved data reliability and integrity in semiconductor memory devices, leading to enhanced overall system performance.

Potential Commercial Applications

This technology can be utilized in the manufacturing of high-performance computing systems, servers, and other memory-intensive applications to ensure data integrity and prevent data loss.

Possible Prior Art

One example of prior art related to this technology is the "Row Hammer" vulnerability discovered in DRAM memory modules, where repeated accesses to the same row can cause bit flips in adjacent rows due to electrical interference.

How does the row hammer management circuit determine which memory cell rows are selected for hammer refresh operations?

The patent application does not provide specific details on the criteria used by the row hammer management circuit to select victim memory cell rows for hammer refresh operations.

What impact does the hammer refresh operation have on the overall performance of the semiconductor memory device?

The patent application does not discuss the potential performance implications of the hammer refresh operation on the semiconductor memory device.

Original Abstract Submitted

a semiconductor memory device includes a memory cell array with a plurality of rows of memory cells therein, and a row hammer management (rhm) circuit including a hammer address queue. the rhm circuit is configured to: (i) receive first access row addresses from an external memory controller during a reference time interval, (ii) store a first row address randomly selected from the first access row addresses and second row addresses consecutively received from the memory controller after selecting the first row address, in the hammer address queue as candidate hammer addresses, and (iii) sequentially output the candidate hammer addresses as a hammer address. a refresh control circuit is provided to receive the hammer address and to perform a hammer refresh operation on one or more victim memory cell rows, which are physically adjacent to a memory cell row corresponding to the hammer address.