Samsung electronics co., ltd. (20240130144). SEMICONDUCTOR PACKAGE INCLUDING A THREE-DIMENSIONAL STACKED MEMORY MODULE simplified abstract

SEMICONDUCTOR PACKAGE INCLUDING A THREE-DIMENSIONAL STACKED MEMORY MODULE

Organization Name

samsung electronics co., ltd.

Inventor(s)

Dong Joo Choi of Suwon-si (KR)

SEMICONDUCTOR PACKAGE INCLUDING A THREE-DIMENSIONAL STACKED MEMORY MODULE - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240130144 titled 'SEMICONDUCTOR PACKAGE INCLUDING A THREE-DIMENSIONAL STACKED MEMORY MODULE

Simplified Explanation

The semiconductor package described in the patent application includes a first redistribution layer with a conductive pattern, connection terminals, a stacked memory module, a second redistribution layer with another conductive pattern, bumps, a semiconductor chip, and a dummy structure.

• The first redistribution layer consists of an insulating layer and a conductive pattern.
• The second redistribution layer is placed on top of the stacked memory module and includes another insulating layer and a conductive pattern.
• The first bump is in contact with the stacked memory module.
• The dummy structure is positioned between the first and second redistribution layers and is spaced apart from the stacked memory module.

Potential Applications

This technology could be applied in:

• Advanced memory modules
• High-performance semiconductor devices

Problems Solved

This innovation addresses:

• Efficient stacking of memory modules
• Improved connectivity in semiconductor packages

Benefits

The benefits of this technology include:

• Enhanced performance in semiconductor devices
• Increased memory capacity in a compact package

Potential Commercial Applications

The potential commercial applications of this technology could be in:

• Consumer electronics
• Data centers

Possible Prior Art

One possible prior art for this technology could be the use of dummy structures in semiconductor packaging to improve performance and connectivity.

How does this technology compare to existing semiconductor packaging solutions?

This technology offers improved connectivity and efficiency in stacking memory modules compared to traditional methods.

What are the manufacturing considerations for implementing this technology on a large scale?

Manufacturing considerations may include the precision required for placing the dummy structure and ensuring proper alignment of the various layers in the semiconductor package.

Original Abstract Submitted

a semiconductor package includes: a first redistribution layer including a first insulating layer and a first conductive pattern disposed in the first insulating layer; a first connection terminal disposed on a first surface of the first redistribution layer; a stacked memory module disposed on second surface of the first redistribution layer; a second redistribution layer disposed on the stacked memory module, and including a second insulating layer and a second conductive pattern disposed in the second insulating layer; a first bump disposed on a first surface of the second redistribution layer, and in contact with the stacked memory module; a first semiconductor chip disposed on second surface of the second redistribution layer; and a dummy structure disposed between the first redistribution layer and the second redistribution layer and spaced apart from the stacked memory module.