Samsung electronics co., ltd. (20240128952). LOW POWER FLIP-FLOP simplified abstract
Contents
LOW POWER FLIP-FLOP
Organization Name
Inventor(s)
Byounggon Kang of Suwon-si (KR)
LOW POWER FLIP-FLOP - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240128952 titled 'LOW POWER FLIP-FLOP
Simplified Explanation
The low power flip-flop described in the patent application includes a master section and a slave section, each containing various gate circuits and inverter circuits. The master section receives input signals and generates internal signals, while the slave section processes these internal signals to produce an output signal. Additionally, the invention includes a circuit for generating an inverted scan enable signal.
- The flip-flop consists of a master section and a slave section, each with specific functions and components.
- The master section receives input signals and generates internal signals, while the slave section processes these internal signals to produce an output signal.
- A circuit is included to generate an inverted scan enable signal, enhancing the functionality of the flip-flop.
Potential Applications
The technology described in this patent application could be applied in various digital systems and integrated circuits where low power consumption is a priority, such as mobile devices, IoT devices, and battery-operated electronics.
Problems Solved
This innovation addresses the challenge of reducing power consumption in flip-flops and other digital circuits, which is crucial for extending battery life in portable devices and improving energy efficiency in electronic systems.
Benefits
The low power flip-flop offers improved energy efficiency, longer battery life, and enhanced performance in digital systems where power consumption is a critical factor. By optimizing power usage, this technology contributes to sustainable and eco-friendly electronic devices.
Potential Commercial Applications
The technology presented in this patent application has potential commercial applications in the semiconductor industry, particularly in the development of low-power integrated circuits for consumer electronics, IoT devices, and other battery-powered devices.
Possible Prior Art
One possible prior art for low power flip-flops is the use of clock gating techniques to reduce power consumption in digital circuits. Additionally, research on low-power design methodologies in integrated circuits may have influenced the development of similar technologies.
Original Abstract Submitted
a low power flip-flop includes a master section including a multiplexer, a first and-or-inverter (aoi) gate circuit, a second aoi gate circuit, and a first inverter circuit and configured to receive a data input signal, a scan input signal, a scan enable signal, and an inverted scan enable signal, and output a second internal signal and a third internal signal, a slave section including a third aoi gate circuit, a fourth aoi gate circuit, and a second inverter circuit, and configured to receive the second and third internal signals to output an output signal, and a third inverter circuit configured to generate the inverted scan enable signal. the first to fourth aoi gate circuits are configured to receive a clock signal.
