Samsung electronics co., ltd. (20240128190). SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME simplified abstract

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Organization Name

samsung electronics co., ltd.

Inventor(s)

Seunghwan Kim of Suwon-si (KR)

Yongkwan Lee of Suwon-si (KR)

Gyuhyeong Kim of Suwon-si (KR)

Jungjoo Kim of Suwon-si (KR)

Jongwan Kim of Suwon-si (KR)

Junwoo Park of Suwon-si (KR)

Taejun Jeon of Suwon-si (KR)

Junhyeung Jo of Suwon-si (KR)

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240128190 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Simplified Explanation

The semiconductor package described in the patent application includes a lower substrate with a lower interconnection layer, an upper substrate with a recessed surface and an upper interconnection layer connected to the lower interconnection layer, a semiconductor chip between the upper substrate and lower substrate with connection pads connected to the lower interconnection layer, an interconnect structure connecting the lower interconnection layer to the upper interconnection layer, and an insulating member covering the semiconductor chip and interconnect structure.

• Lower substrate with lower interconnection layer
• Upper substrate with recessed surface and upper interconnection layer
• Semiconductor chip with connection pads
• Interconnect structure connecting lower and upper interconnection layers
• Insulating member covering semiconductor chip and interconnect structure

Potential Applications

The technology described in the patent application could be applied in various semiconductor packaging applications, such as in microprocessors, memory devices, and integrated circuits.

Problems Solved

This technology solves the problem of efficiently connecting and insulating semiconductor chips within a package, improving overall performance and reliability of the semiconductor device.

Benefits

The benefits of this technology include improved electrical connections, enhanced thermal management, and increased durability of the semiconductor package.

Potential Commercial Applications

The technology could be commercially applied in the manufacturing of consumer electronics, automotive electronics, telecommunications equipment, and industrial machinery.

Possible Prior Art

One possible prior art for this technology could be the use of traditional wire bonding or flip chip technology in semiconductor packaging.

How does this technology compare to existing semiconductor packaging methods?

The article does not provide a direct comparison between this technology and existing semiconductor packaging methods.

What are the specific materials used in this semiconductor package?

The article does not specify the materials used in the semiconductor package.

Original Abstract Submitted

a semiconductor package includes a lower substrate including a lower interconnection layer; an upper substrate on the lower substrate, a recessed surface having a step difference, and an upper interconnection layer having a through-hole extending from the recessed surface to the first surface of the upper substrate and electrically connected to the lower interconnection layer; semiconductor chip between the recessed surface of the upper substrate and the lower substrate and including connection pads electrically connected to the lower interconnection layer; interconnect structure between the second surface of the upper substrate and the lower substrate and electrically connecting the lower interconnection layer to the upper interconnection layer; and an insulating member including a first portion covering at least a portion of the semiconductor chip and interconnect structure, a second portion extending from the first portion into the through-hole, and a third portion covering at least a portion of the first surface.