Samsung electronics co., ltd. (20240113074). SEMICONDUCTOR PACKAGE simplified abstract
Contents
- 1 SEMICONDUCTOR PACKAGE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240113074 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the abstract includes a first substrate with a substrate pad, a first chip stacked structure with multiple chips connected by wires, and a second chip stacked structure with chips offset-stacked in a horizontal direction.
- The semiconductor package includes a first substrate with an upper and lower surface, a substrate pad on the upper surface, and a first chip stacked structure with multiple chips stacked in a first direction.
- The lowermost first wire connects the lowermost first chip to the substrate pad.
- The second chip stacked structure is spaced apart from the first chip stacked structure with the lowermost first wire in between in a horizontal direction.
- The upper surface of the lowermost second chip is at a higher vertical level than the highest level of the lowermost first wire in a vertical direction.
Potential Applications
This technology could be applied in the manufacturing of advanced semiconductor devices, such as microprocessors, memory chips, and integrated circuits.
Problems Solved
This innovation helps in increasing the density of chips in a semiconductor package, improving the overall performance and functionality of electronic devices.
Benefits
The benefits of this technology include higher integration levels, improved signal transmission efficiency, and enhanced overall performance of semiconductor devices.
Potential Commercial Applications
The potential commercial applications of this technology could be in the fields of consumer electronics, telecommunications, automotive electronics, and industrial automation.
Possible Prior Art
One possible prior art for this technology could be the development of 3D chip stacking technology in the semiconductor industry.
Unanswered Questions
How does this technology impact the power consumption of electronic devices?
The article does not provide information on how this technology affects the power consumption of electronic devices.
What are the potential challenges in implementing this technology on a large scale?
The article does not address the potential challenges that may arise in implementing this technology on a large scale.
Original Abstract Submitted
provided is a semiconductor package including a first substrate having an upper surface and a lower surface, and including a substrate pad arranged on the upper surface, a first chip stacked structure mounted on the upper surface of the first substrate, and including a plurality of first chips offset-stacked in a first direction, a lowermost first wire electrically connecting a lowermost first chip to the substrate pad, and a second chip stacked structure mounted on the upper surface of the first substrate, and including a plurality of second chips offset-stacked in the first direction, wherein the second chip stacked structure is spaced apart from the first chip stacked structure with the lowermost first wire therebetween in a horizontal direction, and an upper surface of a lowermost second chip is at a higher vertical direction level than a highest level of the lowermost first wire in a vertical direction.
