Samsung electronics co., ltd. (20240113001). SEMICONDUCTOR PACKAGE simplified abstract
Contents
- 1 SEMICONDUCTOR PACKAGE
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Kyounglim Suk of Suwon-si (KR)
Hyeonjeong Hwang of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240113001 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the abstract includes a complex structure with multiple layers and components for efficient electrical connections and insulation. Here are some key points to explain the patent/innovation:
- The package includes a first redistribution structure with at least one redistribution layer and insulating layer.
- A first semiconductor chip is connected to the redistribution layer and placed on the structure's first surface.
- A second semiconductor chip is positioned on top of the first chip.
- A first encapsulant covers the second surface of the redistribution structure.
- First conductive posts connect to the first semiconductor chip and penetrate the encapsulant.
- Under bump metallurgy (UBM) structures are located beneath the encapsulant, overlapping with the conductive posts and connecting to them.
Potential Applications
This technology can be applied in various electronic devices requiring advanced semiconductor packaging, such as smartphones, tablets, and computers.
Problems Solved
This innovation solves the challenge of efficiently connecting multiple semiconductor chips in a compact package while ensuring proper insulation and electrical conductivity.
Benefits
The semiconductor package offers improved performance, reliability, and miniaturization in electronic devices. It also enables more efficient heat dissipation and signal transmission.
Potential Commercial Applications
The technology can be utilized in the consumer electronics industry for manufacturing high-performance and compact devices, leading to enhanced competitiveness in the market.
Possible Prior Art
One possible prior art could be the use of similar semiconductor packaging techniques in the semiconductor industry to improve device performance and reliability.
Unanswered Questions
How does this technology compare to existing semiconductor packaging methods in terms of cost-effectiveness?
The article does not provide information on the cost implications of implementing this technology compared to traditional semiconductor packaging methods.
What are the environmental impacts of using this advanced semiconductor packaging technology?
The environmental sustainability aspect of this technology is not addressed in the article.
Original Abstract Submitted
a semiconductor package includes: a first redistribution structure including at least one first redistribution layer and at least one first insulating layer; a first semiconductor chip electrically connected to the at least one first redistribution layer and disposed on a first surface of the first redistribution structure; a second semiconductor chip disposed on an upper surface of the first semiconductor chip; a first encapsulant disposed on a second surface of the first redistribution structure opposite the first surface of the first redistribution layer; first conductive posts electrically connected to the first semiconductor chip and penetrating the first encapsulant; and under bump metallurgy (ubm) structures disposed on a lower surface of the first encapsulant, wherein at least a portion of the ubm structures overlap at least a portion of the first conductive posts in a penetration direction of the first conductive posts and are connected to the first conductive posts.
