Samsung electronics co., ltd. (20240112998). SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE simplified abstract
Contents
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Seungkwan Ryu of Suwon-si (KR)
Yanggyoo Jung of Suwon-si (KR)
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240112998 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the patent application includes a package substrate, an interposer mounted on the package substrate via first conductive bumps, first and second semiconductor devices mounted on the interposer via second conductive bumps, and an underfill member filling the space between the first conductive bumps. The interposer has a central region and a peripheral region, with different types of conductive bumps in each region.
- Explanation of the patent:
- Package includes package substrate, interposer, and semiconductor devices - Interposer has central and peripheral regions - Different types of conductive bumps in central and peripheral regions
- Potential applications of this technology:
- Advanced semiconductor packaging - High-performance electronic devices
- Problems solved by this technology:
- Improved thermal performance - Enhanced electrical connectivity
- Benefits of this technology:
- Higher reliability - Increased efficiency
- Potential commercial applications of this technology:
- Consumer electronics - Automotive electronics
- Possible prior art:
- Similar semiconductor packaging techniques using interposers and underfill materials
- Unanswered Questions:
- How does this technology compare to traditional semiconductor packaging methods?
- Unanswered Questions:
This article does not provide a direct comparison between this technology and traditional semiconductor packaging methods. It would be helpful to understand the specific advantages and disadvantages of this approach compared to existing techniques.
- What are the specific manufacturing challenges associated with implementing this semiconductor packaging design?
The article does not delve into the potential manufacturing challenges that may arise when implementing this semiconductor packaging design. Understanding the hurdles in production could provide valuable insights into the feasibility and scalability of this technology.
Original Abstract Submitted
a semiconductor package includes a package substrate, an interposer mounted on the package substrate via first conductive bumps, first and second semiconductor devices disposed spaced apart from each other on the interposer and mounted on the interposer via second conductive bumps, and an underfill member filling a space between the first conductive bumps that are between the package substrate and the interposer. the interposer includes a central region and a peripheral region at least partially surrounding the central region. the first conductive bumps include first bump structures disposed on second bonding pads, which are in the central region and on a lower surface of the interposer, respectively, and having a circular shape. the first conductive bumps further include second bump structures disposed on second bonding pads, which are in the peripheral region and on the lower surface of the interposer, respectively, and having an elliptical shape.
