Samsung electronics co., ltd. (20240112004). METHOD AND APPARATUS WITH 3D IN-MEMORY COMPUTING simplified abstract
Contents
- 1 METHOD AND APPARATUS WITH 3D IN-MEMORY COMPUTING
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 METHOD AND APPARATUS WITH 3D IN-MEMORY COMPUTING - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
METHOD AND APPARATUS WITH 3D IN-MEMORY COMPUTING
Organization Name
Inventor(s)
Seungchul Jung of Suwon-si (KR)
Soon-Wan Kwon of Suwon-si (KR)
METHOD AND APPARATUS WITH 3D IN-MEMORY COMPUTING - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240112004 titled 'METHOD AND APPARATUS WITH 3D IN-MEMORY COMPUTING
Simplified Explanation
The patent application describes an apparatus with a memory layer containing front-end-of-line (FEOL) memory cells and a logic layer with arithmetic logic gates made up of back-end-of-line (BEOL) transistors stacked on top of the memory cells. The BEOL transistors function as multipliers, providing operation results based on values stored in the corresponding memory cells.
- The apparatus includes a memory layer with FEOL memory cells and a logic layer with arithmetic logic gates made of BEOL transistors.
- The BEOL transistors operate as multipliers, generating operation results based on values stored in the memory cells.
Potential Applications
This technology could be applied in:
- High-performance computing systems
- Signal processing applications
- Artificial intelligence and machine learning algorithms
Problems Solved
This technology helps in:
- Increasing computational efficiency
- Reducing power consumption
- Enhancing overall system performance
Benefits
The benefits of this technology include:
- Faster processing speeds
- Improved accuracy in calculations
- Lower energy consumption
Potential Commercial Applications
Optimized for SEO: "Innovative Technology for High-Performance Computing Systems"
- Data centers
- Supercomputers
- Advanced scientific research facilities
Possible Prior Art
There may be prior art related to:
- Memory cell integration with logic gates
- Transistor-based arithmetic logic units
Unanswered Questions
How does this technology compare to traditional computing architectures?
This article does not provide a direct comparison between this technology and traditional computing architectures in terms of performance, efficiency, and scalability.
What are the potential limitations or drawbacks of implementing this technology?
The article does not address any potential limitations or drawbacks that may arise from the implementation of this technology, such as cost, complexity, or compatibility issues.
Original Abstract Submitted
an apparatus including a memory layer including a plurality of front-end-of-line (feol) memory cells and a logic layer including plural arithmetic logic gates including back-end-of-line (beol) transistors, the plurality of beol transistors being vertically stacked on respective upper ends of the plurality of memory cells, wherein each of multiple transistors of the plurality of beol transistors operates as a multiplier and is configured to provide an operation result with respect to first values stored in corresponding memory cells of the plurality of memory cells.
