Samsung electronics co., ltd. (20240105679). SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME simplified abstract

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

Organization Name

samsung electronics co., ltd.

Inventor(s)

YOUNG KUN Jee of Suwon-si (KR)

SANGHOON Lee of Suwon-si (KR)

UN-BYOUNG Kang of Suwon-si (KR)

SANG CHEON Park of Suwon-si (KR)

JUMYONG Park of Suwon-si (KR)

HYUNCHUL Jung of Suwon-si (KR)

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240105679 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

Simplified Explanation

The semiconductor package described in the patent application involves a method of fabricating a semiconductor package by forming a semiconductor element on a substrate, creating vias in the substrate, adding pad layers, and performing planarization processes to ensure a smooth surface.

• Semiconductor package fabrication method:

   * Provide a semiconductor substrate
   * Form a semiconductor element on the active surface
   * Create vias extending into the substrate
   * Add a first pad layer on the active surface
   * Perform a first planarization process
   * Thin the inactive surface to expose vias
   * Add a second pad layer on the inactive surface
   * Perform a second planarization process
   * Perform a third planarization process on the first pad layer

Potential Applications

The technology described in this patent application could be applied in the manufacturing of various semiconductor devices such as microprocessors, memory chips, and sensors.

Problems Solved

This technology addresses the need for improved semiconductor packaging methods that provide better connectivity and reliability for semiconductor devices.

Benefits

The benefits of this technology include enhanced performance, increased durability, and improved signal transmission in semiconductor devices.

Potential Commercial Applications

The semiconductor packaging method outlined in this patent application could be utilized in the production of consumer electronics, automotive components, and industrial machinery.

Possible Prior Art

One possible prior art in semiconductor packaging methods is the use of flip chip technology, which involves flipping the semiconductor die and attaching it to the substrate using solder bumps.

Unanswered Questions

How does this semiconductor packaging method compare to existing methods in terms of cost-effectiveness?

The article does not provide information on the cost implications of implementing this semiconductor packaging method compared to traditional methods.

Are there any limitations or challenges associated with the fabrication process outlined in the patent application?

The article does not address any potential limitations or challenges that may arise during the fabrication process of the semiconductor package.

Original Abstract Submitted

disclosed are semiconductor packages and their fabrication methods. the semiconductor package comprises providing a semiconductor substrate, forming a semiconductor element on an active surface of the semiconductor substrate, forming in the semiconductor substrate through vias that extend from the active surface into the semiconductor substrate, forming a first pad layer on the active surface of the semiconductor substrate, performing a first planarization process on the first pad layer, performing on an inactive surface of the semiconductor substrate a thinning process to expose the through vias, forming a second pad layer on the inactive surface of the semiconductor substrate, performing a second planarization process on the second pad layer, and after the second planarization process, performing a third planarization process on the first pad layer.