Samsung display co., ltd. (20240120342). THIN FILM TRANSISTOR, TRANSISTOR ARRAY SUBSTRATE, AND METHOD FOR FABRICATING THE TRANSISTOR ARRAY SUBSTRATE simplified abstract

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THIN FILM TRANSISTOR, TRANSISTOR ARRAY SUBSTRATE, AND METHOD FOR FABRICATING THE TRANSISTOR ARRAY SUBSTRATE

Organization Name

samsung display co., ltd.

Inventor(s)

Sung Gwon Moon of Yongin-si (KR)

Dong Han Kang of Yongin-si (KR)

Jee Hoon Kim of Yongin-si (KR)

Seung Sok Son of Yongin-si (KR)

Shin Hyuk Yang of Yongin-si (KR)

Woo Geun Lee of Yongin-si (KR)

THIN FILM TRANSISTOR, TRANSISTOR ARRAY SUBSTRATE, AND METHOD FOR FABRICATING THE TRANSISTOR ARRAY SUBSTRATE - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240120342 titled 'THIN FILM TRANSISTOR, TRANSISTOR ARRAY SUBSTRATE, AND METHOD FOR FABRICATING THE TRANSISTOR ARRAY SUBSTRATE

Simplified Explanation

The patent application describes a transistor array substrate with an active layer containing a channel region, a source region, and a drain region. The substrate also includes a gate insulating layer, a gate electrode, a source electrode, and a drain electrode, all of which are part of an electrode conductive layer.

  • The active layer is made of an oxide semiconductor with crystals and is shaped like an island, excluding a hole in a plan view.

Potential Applications:

  • Display technology
  • Integrated circuits

Problems Solved:

  • Improved performance of transistors
  • Enhanced reliability of electronic devices

Benefits:

  • Higher efficiency
  • Lower power consumption

Potential Commercial Applications:

Optimized Technology for Advanced Displays

Possible Prior Art: No prior art known at this time.

Unanswered Questions:

What is the manufacturing cost of implementing this technology?

The article does not provide information on the cost implications of using this technology.

Are there any limitations to the size or scale of devices that can be produced using this technology?

The article does not address any potential limitations on the size or scale of devices that can be manufactured with this technology.


Original Abstract Submitted

a transistor array substrate includes a substrate, an active layer disposed on the substrate and including a channel region, a source region and a drain region, a gate insulating layer disposed on a part of the active layer, a gate electrode overlapping the channel region of the active layer and included in an electrode conductive layer which is disposed on the gate insulating layer, a source electrode included in the electrode conductive layer and in contact with a part of the source region of the active layer, and a drain electrode included in the electrode conductive layer and in contact with a part of the drain region of the active layer. the active layer includes an oxide semiconductor including crystals and is disposed as an island shape excluding a hole in a plan view.