Qualcomm incorporated (20240111934). DESIGN FOR TESTABILITY FOR FAULT DETECTION IN CLOCK GATE CONTROL CIRCUITS simplified abstract
Contents
- 1 DESIGN FOR TESTABILITY FOR FAULT DETECTION IN CLOCK GATE CONTROL CIRCUITS
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 DESIGN FOR TESTABILITY FOR FAULT DETECTION IN CLOCK GATE CONTROL CIRCUITS - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
DESIGN FOR TESTABILITY FOR FAULT DETECTION IN CLOCK GATE CONTROL CIRCUITS
Organization Name
Inventor(s)
Paul Policke of Cedar Park TX (US)
Preston Mcwithey of Austin TX (US)
DESIGN FOR TESTABILITY FOR FAULT DETECTION IN CLOCK GATE CONTROL CIRCUITS - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240111934 titled 'DESIGN FOR TESTABILITY FOR FAULT DETECTION IN CLOCK GATE CONTROL CIRCUITS
Simplified Explanation
The abstract describes an integrated circuit (IC) with cascaded clock gating control (CGC) circuits, observation flip-flop, input register, and test enable control registers for fault testing and control purposes.
- The IC includes a set of cascaded CGC circuits for clock gating control.
- The first CGC circuit has a clock input for receiving a clock signal.
- An observation flip-flop is included with its clock input connected to the last CGC circuit's clock output.
- An input register provides logic zeros to CGC circuits for stuck-at-one fault testing.
- Test enable control registers provide logic ones to CGC circuits not undergoing fault testing.
Potential Applications
The technology described in the patent application could be applied in various digital systems where clock gating control and fault testing are essential, such as microprocessors, digital signal processors, and other integrated circuits.
Problems Solved
1. Efficient clock gating control to reduce power consumption in digital systems. 2. Facilitates fault testing for stuck-at-one faults in CGC circuits.
Benefits
1. Improved power efficiency in digital systems. 2. Enhanced fault testing capabilities for CGC circuits. 3. Increased reliability and robustness of integrated circuits.
Potential Commercial Applications
Optimizing power consumption in mobile devices, improving performance in high-speed processors, enhancing reliability in safety-critical systems.
Possible Prior Art
Prior art may include patents or publications related to clock gating control circuits, fault testing methodologies in integrated circuits, and design techniques for improving power efficiency in digital systems.
Unanswered Questions
How does the technology impact overall system performance?
The article does not delve into the specific performance metrics affected by the described technology, such as speed, power consumption, or reliability.
Are there any limitations or drawbacks to this technology?
The potential limitations or drawbacks of the technology, such as increased complexity, area overhead, or impact on system latency, are not discussed in the article.
Original Abstract Submitted
an integrated circuit (ic), including: a set of cascaded clock gating control (cgc) circuits, wherein a first one of the set of cascaded cgc circuits includes a clock input configured to receive a clock signal; an observation flip-flop including a clock input coupled to a clock output of a last one of the set of cascaded cgc circuits; an input register configured to provide logic zeros (0s) to clock enable (ce) inputs of the set of cascaded cgc circuits pursuant to a stuck-at-one (sa1) fault testing on the ce input of a selected one of the set of cascaded cgc circuits; and a set of one or more test enable (te) control registers configured to provide one or more logic ones (1s) to one or more te inputs of one or more of the set of cascaded cgc circuits not undergoing the stuck-at-one (sa1) fault testing, respectively.
