Qualcomm incorporated (20240111700). LATENCY REDUCTION FOR LINK SPEED SWITCHING IN MULTIPLE LANE DATA LINKS simplified abstract

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LATENCY REDUCTION FOR LINK SPEED SWITCHING IN MULTIPLE LANE DATA LINKS

Organization Name

qualcomm incorporated

Inventor(s)

Prakhar Srivastava of Lucknow (IN)

Santhosh Reddy Akavaram of Hyderabad (IN)

Ravindranath Doddi of Hyderabad (IN)

Ravi Kumar Sepuri of Hyderabad (IN)

LATENCY REDUCTION FOR LINK SPEED SWITCHING IN MULTIPLE LANE DATA LINKS - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240111700 titled 'LATENCY REDUCTION FOR LINK SPEED SWITCHING IN MULTIPLE LANE DATA LINKS

Simplified Explanation

The patent application abstract describes an apparatus that includes an interface circuit for a multiple lane data link, with the ability to change data rates and transfer data traffic between different sets of lanes.

  • The apparatus includes an interface circuit for a multiple lane data link.
  • The data link has a first set of lanes in an active state and a second set of lanes in an idle state.
  • The controller can receive a request to change the data rate of the data link.
  • The second set of lanes can be changed from idle to active state and trained to the requested data rate.
  • Data traffic can be transferred from the first set of lanes to the second set after training.
  • The data traffic can then be transmitted on the second set of lanes.

Potential Applications

This technology could be applied in high-speed data transfer systems, such as computer peripherals, networking devices, and data storage systems.

Problems Solved

This innovation addresses the need for efficient data transfer at different data rates within a multiple lane data link, improving overall system performance and reliability.

Benefits

The benefits of this technology include increased data transfer speeds, optimized data traffic management, and enhanced system flexibility for adapting to varying data rate requirements.

Potential Commercial Applications

Potential commercial applications for this technology include high-speed networking equipment, data storage solutions, and advanced computing devices.

Possible Prior Art

One possible prior art could be related to similar technologies used in high-speed data transfer systems, such as PCIe interfaces and data link protocols.

Unanswered Questions

How does the apparatus handle data traffic congestion within the multiple lane data link?

The abstract does not provide details on how the apparatus manages data traffic congestion or prioritizes data traffic within the multiple lane data link.

What measures are in place to ensure data integrity during the data rate change and lane training processes?

The abstract does not mention any specific mechanisms or protocols that guarantee data integrity when changing data rates and training lanes within the data link.


Original Abstract Submitted

aspects relate to link speed for a peripheral component interconnect. in one aspect, an apparatus includes an interface circuit configured to provide an interface with a multiple lane data link, the data link having a first set of lanes in an active state and a second set of lanes in an idle state and a controller. the controller is configured to receive a request at the controller to change a data rate of the data link to a requested data rate, change the second set of lanes from an idle state to an active state, train the second set of lanes to the requested data rate, transfer data traffic from the first set of lanes to the second set of lanes after the training, and transmit the data traffic on the second set of lanes.