Qualcomm incorporated (20240111424). REDUCING LATENCY IN PSEUDO CHANNEL BASED MEMORY SYSTEMS simplified abstract
Contents
- 1 REDUCING LATENCY IN PSEUDO CHANNEL BASED MEMORY SYSTEMS
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 REDUCING LATENCY IN PSEUDO CHANNEL BASED MEMORY SYSTEMS - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
REDUCING LATENCY IN PSEUDO CHANNEL BASED MEMORY SYSTEMS
Organization Name
Inventor(s)
Shyamkumar Thoziyoor of San Diego CA (US)
Pankaj Deshmukh of San Diego CA (US)
Jungwon Suh of San Diego CA (US)
Subbarao Palacharla of San Diego CA (US)
REDUCING LATENCY IN PSEUDO CHANNEL BASED MEMORY SYSTEMS - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240111424 titled 'REDUCING LATENCY IN PSEUDO CHANNEL BASED MEMORY SYSTEMS
Simplified Explanation
The patent application describes methods and devices for reducing latency in pseudo-channel based memory systems. This includes selecting pseudo channels to connect to input/output devices concurrently, using data buses to implement memory access commands.
- Pseudo-channel selection devices connect pseudo channels to input/output devices concurrently.
- Memory system receives memory access commands targeting specific pseudo channels and uses data buses to execute commands.
Potential Applications
This technology could be applied in high-performance computing systems, data centers, and other memory-intensive applications where reducing latency is crucial.
Problems Solved
This technology solves the problem of latency in memory systems, improving overall system performance and efficiency.
Benefits
The benefits of this technology include faster data access, improved system responsiveness, and enhanced overall performance in memory-intensive applications.
Potential Commercial Applications
Potential commercial applications of this technology include server systems, supercomputers, cloud computing infrastructure, and any other systems where memory access speed is critical.
Possible Prior Art
One possible prior art could be the use of multi-channel memory architectures in computer systems to improve memory access speeds.
Unanswered Questions
1. How does this technology compare to existing memory optimization techniques? 2. What impact could this technology have on the overall cost of memory systems?
Original Abstract Submitted
various embodiments include methods and devices for reducing latency in pseudo channel based memory systems. embodiments may include a first pseudo channel selection device configured to selectively communicatively connect one of a plurality of pseudo channels to a first input/output (io), and a second pseudo channel selection device configured to selectively communicatively connect one of the plurality of pseudo channels to a second io, in which the first pseudo channel selection device and the second pseudo channel selection device may be operable to communicatively connect a first pseudo channel of the plurality of pseudo channels to the first io and to the second io concurrently. embodiments may include the pseudo channel based memory system configured to receive a memory access command targeting the first pseudo channel, and use a first pseudo channel data bus and a second pseudo channel data bus to implement the memory access command.
