Nvidia corporation (20240096802). REVERSE EMBEDDED POWER STRUCTURE FOR GRAPHICAL PROCESSING UNIT CHIPS AND SYSTEM-ON-CHIP DEVICE PACKAGES simplified abstract

REVERSE EMBEDDED POWER STRUCTURE FOR GRAPHICAL PROCESSING UNIT CHIPS AND SYSTEM-ON-CHIP DEVICE PACKAGES

Organization Name

nvidia corporation

Inventor(s)

Shawn Xiao of Santa Clara CA (US)

Justin Jiang of Santa Clara CA (US)

Henry Li of Santa Clara CA (US)

Jerry Zhou of Santa Clara CA (US)

Joey Jiao of Santa Clara CA (US)

REVERSE EMBEDDED POWER STRUCTURE FOR GRAPHICAL PROCESSING UNIT CHIPS AND SYSTEM-ON-CHIP DEVICE PACKAGES - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240096802 titled 'REVERSE EMBEDDED POWER STRUCTURE FOR GRAPHICAL PROCESSING UNIT CHIPS AND SYSTEM-ON-CHIP DEVICE PACKAGES

Simplified Explanation

The abstract describes a die for an integrated circuit package, including interconnect layers, transistors, and power regions.

• Die for integrated circuit package:

   - Includes interconnect layers with metal lines and vias
   - Transistor region with electrical connections to power rails
   - Power region with electro-conductive film and through-silicon vias (TSVs)

• Method of manufacturing an IC package and computer with the IC package are also disclosed.

Potential Applications

This technology can be applied in various electronic devices requiring integrated circuits, such as smartphones, tablets, laptops, and other consumer electronics.

Problems Solved

This technology solves the problem of efficiently connecting different components within an integrated circuit package, improving performance and reliability.

Benefits

- Enhanced electrical connections between components - Improved power distribution and management - Increased overall performance and efficiency of the integrated circuit package

Potential Commercial Applications

"Die for Integrated Circuit Package: Applications in Electronics Industry"

Possible Prior Art

There may be prior art related to the integration of interconnect layers, transistors, and power regions within an integrated circuit package. Further research is needed to identify specific examples.

Unanswered Questions

How does this technology impact the overall size of the integrated circuit package?

The abstract does not provide information on whether this technology affects the size of the integrated circuit package.

What materials are used in the manufacturing process of this die?

The abstract does not specify the materials used in the manufacturing process of this die.

Original Abstract Submitted

a die including a die body having a first body surface, a second body surface on an opposite side of the die body as the first body surface, an interconnect region adjacent to the first body surface including interconnect dielectric layers with metal lines and vias, a transistor region above the interconnect region, the metal lines and vias making electrical connections to one or more power rails of the transistor region and electrically connected to transistors of the transistor region, a power region above the transistor region including an electro-conductive film on the second body surface and tsvs in the power region, an outer end of the tsv contacting the film and an embedded end of the tsvs contacting one of the power rails. a method of manufacturing an ic package and computer with the ic package are also disclosed.