Micron technology, inc. (20240130132). ELECTRONIC DEVICES INCLUDING PILLARS IN ARRAY REGIONS AND NON-ARRAY REGIONS simplified abstract

ELECTRONIC DEVICES INCLUDING PILLARS IN ARRAY REGIONS AND NON-ARRAY REGIONS

Organization Name

micron technology, inc.

Inventor(s)

S M Istiaque Hossain of Boise ID (US)

Christopher J. Larsen of Boise ID (US)

Anikumar Chandolu of Boise ID (US)

Wesley O. Mckinsey of Nampa ID (US)

Tom J. John of Boise ID (US)

Arun Kumar Dhayalan of Boise ID (US)

Prakash Rau Mokhna Rau of Boise ID (US)

ELECTRONIC DEVICES INCLUDING PILLARS IN ARRAY REGIONS AND NON-ARRAY REGIONS - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240130132 titled 'ELECTRONIC DEVICES INCLUDING PILLARS IN ARRAY REGIONS AND NON-ARRAY REGIONS

Simplified Explanation

The electronic device described in the patent application consists of a lower deck and an upper deck, each comprising tiers of alternating conductive and dielectric materials. Memory pillars are present in the array region of both decks, while dummy pillars and additional conductive material are present in the non-array regions.

• Memory pillars in lower and upper decks are operably coupled to a source.
• Dummy pillars in the upper deck of non-array regions are electrically isolated from the source.
• Additional conductive material is present in the non-array regions of both decks.

Potential Applications

The technology described in this patent application could be applied in the development of advanced memory devices, such as non-volatile memory or solid-state drives.

Problems Solved

This technology addresses the need for efficient and reliable electronic devices with improved memory storage capabilities.

Benefits

The benefits of this technology include enhanced memory performance, increased data storage capacity, and potentially lower power consumption.

Potential Commercial Applications

The technology could find applications in the consumer electronics industry, data storage sector, and other fields requiring high-performance memory devices.

Possible Prior Art

One possible prior art for this technology could be the development of similar memory devices with tiered structures of conductive and dielectric materials, although the specific configuration of memory and dummy pillars may be unique to this patent application.

How does this technology compare to existing memory devices on the market?

This article does not provide a direct comparison between this technology and existing memory devices in terms of performance, reliability, or cost.

What are the potential challenges in scaling up production of electronic devices using this technology?

The article does not address the potential challenges in scaling up production of electronic devices incorporating this technology, such as manufacturing complexity or cost implications.

Original Abstract Submitted

an electronic device comprising a lower deck and an upper deck adjacent to a source. each of the lower deck and the upper deck comprise tiers of alternating conductive materials and dielectric materials. each of the lower deck and the upper deck also comprise an array region and one or more non-array regions. memory pillars are in the lower deck and the upper deck of the array region and the memory pillars are configured to be operably coupled to the source. dummy pillars are in the upper deck of the one or more non-array regions and the dummy pillars are configured to be electrically isolated from the source. another conductive material is in the upper deck and the lower deck of the one or more non-array regions. additional electronic devices and related systems and methods of forming an electronic device are also disclosed.