Micron technology, inc. (20240127901). TEMPERATURE-BASED ERROR MASKING DURING MBIST OPERATION simplified abstract
Contents
- 1 TEMPERATURE-BASED ERROR MASKING DURING MBIST OPERATION
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 TEMPERATURE-BASED ERROR MASKING DURING MBIST OPERATION - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
TEMPERATURE-BASED ERROR MASKING DURING MBIST OPERATION
Organization Name
Inventor(s)
Daniel S. Miller of Boise ID (US)
Yoshinori Fujiwara of Boise ID (US)
TEMPERATURE-BASED ERROR MASKING DURING MBIST OPERATION - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240127901 titled 'TEMPERATURE-BASED ERROR MASKING DURING MBIST OPERATION
Simplified Explanation
The abstract describes methods, apparatuses, and systems related to masking self-test results in a memory device when the temperature exceeds a threshold.
- Memory device includes a self-test circuit
- Self-test circuit suspends collection of test results when temperature exceeds threshold
Potential Applications
This technology could be applied in various electronic devices that use memory devices, such as computers, smartphones, and tablets.
Problems Solved
This technology solves the problem of inaccurate self-test results due to high temperatures in memory devices.
Benefits
The benefits of this technology include improved reliability and accuracy of self-test results in memory devices, leading to better overall performance and longevity of the devices.
Potential Commercial Applications
A potential commercial application of this technology could be in the manufacturing of electronic devices to ensure high quality and reliability of memory devices used in the products.
Possible Prior Art
One possible prior art could be the use of temperature sensors in electronic devices to monitor and control temperature levels to prevent overheating and potential damage to the components.
What are the specific temperature thresholds used in this technology?
The specific temperature thresholds used in this technology are not mentioned in the abstract. Further details may be provided in the full patent application.
How does the self-test circuit selectively suspend collection of test results?
The abstract does not provide specific details on how the self-test circuit selectively suspends collection of test results. This information may be elaborated on in the detailed description of the patent application.
Original Abstract Submitted
methods, apparatuses, and systems related to masking of self-test results are described. a memory device may include a self-test circuit that is configured to selectively suspend collection of test results from one or more portions of a self-test when a temperature of the memory device exceeds a temperature threshold.
