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| − | '''Summary of the patent applications from Micron Technology, Inc. on October 5th, 2023'''
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| − | Micron Technology, Inc. has recently filed patents related to memory arrays, memory devices and systems, memory circuits, transistors, amplifiers, semiconductor structures, and microelectronic devices. These patents focus on the structure and construction of these technologies, rather than specific methods or processes. Notable applications of these patents include:
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| − | * Memory arrays consisting of strings of memory cells organized into memory blocks, with insulative and conductive tiers separating the blocks.
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| − | * Memory devices and systems with memory strings that have a conductor channel shell and a low dielectric constant central region.
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| − | * Memory circuits with memory cells arranged in strings, connected to a conductor tier through channel-material strings passing through insulative and conductive tiers.
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| − | * Transistors with antimony-gallium-zinc-oxide (SbGZO) channel regions.
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| − | * Amplifiers with two stages, including a floating current source and a local common mode feedback in the first stage, and a driver supplying load current in the second stage.
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| − | * Semiconductor structures with device structures on a substrate, each having sidewall spacers consisting of liner layers, oxide spacers, and etch stop layers.
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| − | * Microelectronic devices with stack structures made up of insulative and conductive layers arranged in tiers, with different stadiums containing different numbers of staircase sets.
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| − | Overall, Micron Technology, Inc. has filed patents for various memory-related technologies, including memory arrays, devices, and circuits, as well as patents for transistors, amplifiers, semiconductor structures, and microelectronic devices. These patents focus on the structure and construction of these technologies, with potential applications in memory storage, data processing, and electronic systems.
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| | ==Patent applications for Micron Technology, Inc. on October 5th, 2023== | | ==Patent applications for Micron Technology, Inc. on October 5th, 2023== |
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| | '''Inventor''' | | '''Inventor''' |
| | Alex Frolikov | | Alex Frolikov |
| − |
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| − | '''Brief explanation'''
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| − | This abstract describes a computer storage device that includes a host interface, a controller, non-volatile storage media, and firmware. The firmware provides instructions to the controller for various tasks. In this case, it instructs the controller to receive a request from a host to allocate a specific amount of non-volatile memory. In response to this request, the firmware generates a namespace map that identifies blocks of addresses with a predetermined size, as well as a partial block with a smaller size. The firmware then uses this namespace map to convert logical addresses provided by the host into physical addresses for the allocated memory. The request for allocating the namespace can be made using the NVMe protocol.
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| − | '''Abstract'''
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| − | A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: receive, via the host interface, a request from a host to allocate a namespace of a quantity of non-volatile memory; generate, in response to the request, a namespace map identifying a plurality of blocks of addresses having a same predetermined block size, and a partial block of addresses having a size smaller than the predetermined block size; and convert, using the namespace map, logical addresses in the namespace communicated from the host to physical addresses for the quantity of the non-volatile memory. For example, the request for allocating the namespace can be in accordance with an NVMe protocol.
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| | ===DYNAMIC MEMORY DEVICE MANAGEMENT AND STREAM PRIORITIZATION BASED ON QUALITY OF SERVICE METRICS (17708811)=== | | ===DYNAMIC MEMORY DEVICE MANAGEMENT AND STREAM PRIORITIZATION BASED ON QUALITY OF SERVICE METRICS (17708811)=== |
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| | '''Inventor''' | | '''Inventor''' |
| | Manjunath Chandrashekaraiah | | Manjunath Chandrashekaraiah |
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| − | '''Brief explanation'''
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| − | This abstract describes methods, devices, and systems for managing the performance of a memory device. It introduces a quality-of-service (QoS) processor that negotiates a configuration policy with hosts and communicates it to the memory device. The QoS processor then monitors the workload of the memory device, which consists of requests from the hosts for specific computing operations. It classifies the workload by comparing it to the memory device's execution parameters and computes a projected QoS based on this classification. Finally, the QoS processor updates the configuration policy using the projected QoS.
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| − | '''Abstract'''
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| − | Exemplary methods, apparatuses, and systems including a quality-of-service (QoS) processor for managing performance of a memory device. The QoS processor negotiates a configuration policy with one or more hosts. The QoS processor communicates the configuration policy to a memory device. The QoS processor monitors a workload of the memory device, the workload including one or more requests from the one or more hosts for the memory device to perform a type of computing operation. The QoS processor classifies the workload by comparing the workload to execution parameters of the memory device. The QoS processor computes a projected QoS using the classification of the workload. The QoS processor updates the configuration policy using the projected QoS.
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| | ===ALIGNMENT OF ACTIVATION PERIODS (17708627)=== | | ===ALIGNMENT OF ACTIVATION PERIODS (17708627)=== |
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| | '''Inventor''' | | '''Inventor''' |
| | Liang Ge | | Liang Ge |
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| − | '''Brief explanation'''
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| − | The abstract describes methods, systems, and devices for aligning activation periods. It also discusses techniques for memory operations. The device can transition from a low-power state to a reception-ready state based on a timing parameter. This timing parameter indicates the duration it takes for the device to transition from the low-power state to the reception-ready state. Once in the reception-ready state, the device can receive data transmissions starting at a specific time. If there is an error in the data transmission, a second time associated with the error is determined. The timing parameter can be adjusted to indicate a different duration for transitioning the device to the reception-ready state based on the difference between the second time and the first time.
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| − |
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| − | '''Abstract'''
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| − | Methods, systems, and devices for alignment of activation periods are described. Techniques for memory operations are described. A device may transition from a reduced-power state to a reception-ready state based on a timing parameter of the device that indicates a first duration for transitioning the device from the reduced-power state to the reception-ready state. After transitioning to the reception-ready state, a data transmission may be received beginning at a first time. A second time associated with an error in the data transmission may be determined. The timing parameter may be configured to indicate a second duration for transitioning the device to the reception-ready state based on a difference between the second time and the first time.
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| | ===READING A MASTER BOOT RECORD FOR A NAMESPACE AFTER REFORMATTING THE NAMESPACE (17708828)=== | | ===READING A MASTER BOOT RECORD FOR A NAMESPACE AFTER REFORMATTING THE NAMESPACE (17708828)=== |
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| | '''Inventor''' | | '''Inventor''' |
| | Alexei Frolikov | | Alexei Frolikov |
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| − | '''Brief explanation'''
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| − | This abstract describes a method for managing memory devices. It involves formatting a memory with a specific structure, writing data to a designated region outside of that structure, and then reformatting the memory with a different structure. When a read command is received for a specific address range, the data from the designated region is read, padded, and sent to the requesting device.
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| − | '''Abstract'''
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| − | Systems, methods, and apparatus related to memory devices. In one approach, a memory has a namespace formatted using a first sector size. Master boot record (MBR) data is written to an MBR region outside of the namespace using the first sector size. After writing the MBR data, the namespace is reformatted using a second sector size. A read command is received from a host for an address in an MBR address range of the namespace. In response to receiving the read command, the MBR data is read from the MBR region. Padding is added to the read MBR data, and the padded MBR data is sent to the host device.
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| | ===TECHNIQUES FOR TEMPERATURE-BASED ACCESS OPERATIONS (17711439)=== | | ===TECHNIQUES FOR TEMPERATURE-BASED ACCESS OPERATIONS (17711439)=== |
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| | '''Inventor''' | | '''Inventor''' |
| | Olivier Duval | | Olivier Duval |
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| − | '''Brief explanation'''
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| − | This abstract describes methods, systems, and devices for temperature-based access operations in a memory system. During a write operation, temperature information is written to metadata, indicating the temperature range within which the memory system is operating. This temperature information is then used during read operations, along with the current temperature of the memory system, to perform the corresponding read operation. A server can determine and provide parameters for writing the temperature information to the metadata, as well as trim parameters for read operations based on temperature information received from the memory system. The memory system can also perform targeted refresh operations at specific locations based on temperature information stored with those locations.
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| − | '''Abstract'''
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| − | Methods, systems, and devices for techniques for temperature-based access operations are described. A memory system may be configured to write temperature information to metadata during a write operation. The temperature information may indicate a temperature range within which the memory system may be during the write operation. The memory system may perform a corresponding read operation based on the temperature information written to the metadata and a temperature of the memory system during the read operation. A server may determine and indicate parameters associated with writing the temperature information to the metadata. Additionally, or alternatively, the server may indicate trim parameters for use in performing read operations based on temperature information received from the memory system. In some examples, the memory system may perform targeted refresh operations at locations based on temperature information stored associated with the locations.
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| | ===Programming a Coarse Grained Reconfigurable Array through Description of Data Flow Graphs (17705099)=== | | ===Programming a Coarse Grained Reconfigurable Array through Description of Data Flow Graphs (17705099)=== |
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| | '''Inventor''' | | '''Inventor''' |
| | Skyler Arron Windh | | Skyler Arron Windh |
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| − | '''Brief explanation'''
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| − | The abstract describes an assembly language program designed for a specific type of computer architecture called a coarse grained reconfiguration array (CGRA). The program includes information about the operations to be performed using the dispatch interface and memory interfaces of the CGRA. It also includes details about memory variables that refer to specific memory locations in the CGRA's tile memories. The program is designed to specify one or more synchronous data flows through these memory locations, using the input provided, in order to produce a desired result using the CGRA.
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| − | '''Abstract'''
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| − | An assembly language program for a coarse grained reconfiguration array (CGRA), having dispatch interface information indicating operations to be performed via a dispatch interface of the CGRA to receive an input, memory interface information indicating operations to be performed via one or more memory interfaces of the CGRA, tile memory information indicating memory variables referring to memory locations to be implemented in tile memories of the CGRA, a flow description specifying one or more synchronous data flows, through the memory locations referenced via the memory variables in the tile memory information, to produce a result from the input using the CGRA.
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| | ===SYSTEMS AND METHODS FOR ADDRESS FAULT DETECTION (17711002)=== | | ===SYSTEMS AND METHODS FOR ADDRESS FAULT DETECTION (17711002)=== |
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| | '''Inventor''' | | '''Inventor''' |
| | Melissa I. Uribe | | Melissa I. Uribe |
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| − | '''Brief explanation'''
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| − | The abstract describes a memory device that has a system to detect errors in the addresses used to store and read data. This system generates a parity bit from the address and either stores it with the data or uses it to adjust error correction bits. By analyzing the resulting error correction bits, the system can determine if there was an address error and raise a flag to indicate it.
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| − | '''Abstract'''
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| − | A memory device is provided. The memory device includes a memory bank configured to store data in one or more memory cells. The memory device further includes an address fault detection system designed to detect a mismatch between the address originally used to store the data and the address subsequently used to read the data. The address fault detection system generates an address parity bit from the received address and either stores that address parity bit with the user data or uses the address parity bit to invert the internal ECC bits generated from the user data. The address fault detection system can determine from the resulting syndrome from the ECC bits whether or not an address fault has occurred and raise an address fault indication flag if the address fault is detected.
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| | ===SCRUB OPERATIONS WITH ROW ERROR INFORMATION (17657575)=== | | ===SCRUB OPERATIONS WITH ROW ERROR INFORMATION (17657575)=== |
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| | '''Inventor''' | | '''Inventor''' |
| | Sujeet V. Ayyapureddi | | Sujeet V. Ayyapureddi |
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| − | '''Brief explanation'''
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| − | This abstract describes methods, systems, and devices for performing scrub operations on a memory device. During a scrub operation, the memory device reads data and error control information stored in a row of the memory array and detects the number of errors in that row. The memory device then stores this error count in the memory cells associated with the data in that row. Based on the detected errors, the memory device determines that the reliability of the row has decreased. As a result, the memory device reconfigures the memory array to store the data of the row in another row.
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| − | '''Abstract'''
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| − | Methods, systems, and devices for scrub operations with row error information are described. A memory device may include a memory array with a set of rows. During a scrub operation, the memory device may read data and error control information stored in a row of the memory array and detect a quantity of errors in the row. The memory device may store the quantity of detected errors in the row of the memory device during the scrub operation in memory cells of the memory array storing data associated with the row of the memory array. In some cases, the memory device may then determine that the row is associated with a decreased reliability based on the stored quantity of errors detected in the row during the scrub operation. Here, the memory device may reconfigure the memory array to store the data of the row in another row.
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| | ===CRYPTOGRAPHIC DATA INTEGRITY PROTECTION (18206398)=== | | ===CRYPTOGRAPHIC DATA INTEGRITY PROTECTION (18206398)=== |
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| | '''Inventor''' | | '''Inventor''' |
| | David Aaron Palmer | | David Aaron Palmer |
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| − | '''Brief explanation'''
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| − | This abstract describes a storage device that has a memory storage region and a controller with a processor. The processor retrieves user data from the memory storage region using a physical block address that corresponds to a logical block address (LBA) when a read command is given. The retrieved user data includes a first hash that was received through a host interface in a previous data transmission. The processor also performs error correction on the user data to generate error-corrected user data. Additionally, the processor instructs a cryptographic engine to create a second hash of the error-corrected user data. The first hash is then compared to the second hash associated with the error-corrected user data to determine if they match. If there is a match, a notification is generated.
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| − | '''Abstract'''
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| − | A storage device includes a memory storage region and a controller having a processor. The processor retrieves user data from the memory storage region using a physical block address corresponding to a logical block address (LBA), in response to a read command. The retrieved user data includes a first hash received through a host interface in a prior host data transmission. The processor further performs error correction on the user data to generate error-corrected user data. The processor further causes a cryptographic engine to produce a second hash of the error-corrected user data. The first hash is compared to the second hash associated with the error-corrected user data to determine a match result. A notification is generated in response to the match result.
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| | ===ERROR CORRECTION WITH SYNDROME COMPUTATION IN A MEMORY DEVICE (18329886)=== | | ===ERROR CORRECTION WITH SYNDROME COMPUTATION IN A MEMORY DEVICE (18329886)=== |
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| | '''Inventor''' | | '''Inventor''' |
| | Mustafa N. KAYNAK | | Mustafa N. KAYNAK |
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| − | '''Brief explanation'''
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| − | This abstract describes a method for error correction in a memory device. It explains that a syndrome, which is a type of error detection code, is generated for encoded data in the memory device. This syndrome, along with the encoded data, is sent to a controller. Another syndrome is generated for a combination of two encoded data sets, and this second syndrome is sent to the controller without the actual encoded data. The controller then uses these syndromes to decode the first encoded data.
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| − | '''Abstract'''
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| − | Methods, systems, and apparatus for error correction with syndrome computation in a memory device are described. A first syndrome for first encoded data is generated in a memory device. The first syndrome and the first encoded data are transmitted to a controller that is coupled with the memory device. A second syndrome for first and second encoded data is generated. The first encoded data and the second encoded data are interrelated according to an error correction code. The second syndrome is transmitted to the controller without the second encoded data and the controller is to decode the first encoded data based on at least one of the first syndrome, the second syndrome, or a combination thereof.
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| | ===EVALUATION OF MEMORY DEVICE HEALTH MONITORING LOGIC (18156594)=== | | ===EVALUATION OF MEMORY DEVICE HEALTH MONITORING LOGIC (18156594)=== |
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| | '''Inventor''' | | '''Inventor''' |
| | Scott E. Schaefer | | Scott E. Schaefer |
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| − | '''Brief explanation'''
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| − | The abstract describes methods, systems, and devices for evaluating the health monitoring logic of a memory device. The memory device has a configuration that produces an expected output regardless of its degradation level. This configuration can be enabled in a test mode, allowing the memory device or a host device connected to it to compare the expected output with the actual output of the health monitoring logic. If the actual output matches the expected output, it indicates that the health monitoring logic is functioning correctly. If the actual output differs from the expected output, it suggests that there may be a malfunction in the health monitoring logic.
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| − | '''Abstract'''
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| − | Methods, systems, and devices for evaluation of memory device health monitoring logic are described. A memory device may include health monitoring logic that is operable to be enabled in a configuration that corresponds to an output, such as an expected output, regardless of a degradation level of the memory device. Such a configuration may be enabled in a mode, such as a test mode, during which the memory device, or a host device coupled with the memory device, or some combination, may evaluate a difference between the output and an actual output of the health monitoring logic. The actual output being the same as the output may provide an indication that at least a portion of the health monitoring logic is functioning properly, and the actual output being different than the output may provide an indication that at least a portion of the health monitoring logic is not functioning properly.
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| | ===SELF-SEEDED RANDOMIZER FOR DATA RANDOMIZATION IN FLASH MEMORY (18206958)=== | | ===SELF-SEEDED RANDOMIZER FOR DATA RANDOMIZATION IN FLASH MEMORY (18206958)=== |
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| | '''Inventor''' | | '''Inventor''' |
| | Zhengang Chen | | Zhengang Chen |
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| − | '''Brief explanation'''
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| − | The abstract describes methods, systems, devices, and mediums that allow for efficient internal copyback operations by scrambling and updating meta-data. These techniques involve decoupling the scrambling key from a physical address in order to maintain data distribution requirements across a memory device. A controller generates a seed value that is used by a scrambling algorithm to scramble the host-data and meta-data before it is written. The seed value is then encoded and written to the page along with encoded versions of the scrambled user data and meta-data, without scrambling the seed value itself.
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| − | '''Abstract'''
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| − | Disclosed in some examples are methods, systems, devices, and machine-readable mediums that provide for techniques for scrambling and/or updating meta-data that enable an efficient internal copyback operation. In some examples, improved data distribution techniques decouple the scrambling key from a physical address to allow for copyback operations while maintaining data distribution requirements across a memory device. The controller may generate a seed value that is used by a scrambling algorithm to scramble the host-data and meta-data prior to the data being written. The seed value is then encoded and written to the page with encoded versions of the scrambled user data and meta-data—the random seed is written without scrambling the random seed.
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| | ===UNUSED REDUNDANT ENABLE DISTURB PROTECTION CIRCUIT (17706410)=== | | ===UNUSED REDUNDANT ENABLE DISTURB PROTECTION CIRCUIT (17706410)=== |
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| | '''Inventor''' | | '''Inventor''' |
| | Seth A. Eichmeyer | | Seth A. Eichmeyer |
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| − | '''Brief explanation'''
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| − | The abstract describes a memory device that has multiple fuse banks to store information about memory addresses. These fuse banks store information about default addresses or addresses of defective memory cells. There is a circuit in the device that checks if a fuse bank is storing information about both the default address and a defective memory cell address. If no fuse bank has this information, the device includes a circuit that prevents the repair of an external memory address if it matches the default address.
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| − | '''Abstract'''
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| − | A memory device includes a plurality of fuse banks for a memory region. Each fuse bank stores bit information that relates to at least one of a default address for the plurality of fuse banks or an address of a memory cell that is defective. A default address protection circuit is configured to provide a default address status signal indicating whether a fuse bank in the plurality of fuse banks is storing bit information that corresponds to both the default address and an address of a memory cell that is defective. The memory device include a no_match circuit that overrides a repair of the external memory address if the external address matches the default address and if the default address status signal indicates that no fuse bank is storing bit information that corresponds to both the default address and an address of a memory cell that is defective.
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| | ===LOW POWER MANAGEMENT FOR SLEEP MODE OPERATION OF A MEMORY DEVICE (17426963)=== | | ===LOW POWER MANAGEMENT FOR SLEEP MODE OPERATION OF A MEMORY DEVICE (17426963)=== |
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| | '''Inventor''' | | '''Inventor''' |
| | Shuai Xu | | Shuai Xu |
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| − | '''Brief explanation'''
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| − | The abstract describes a method for putting a memory device into a sleep mode while keeping the power supply of the memory system on. This is achieved by activating a standby circuit that provides a low power mode for the memory device. The standby circuit supplies a reference voltage to a voltage regulator, which in turn supplies a low level of current to the memory device during the sleep mode.
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| − | '''Abstract'''
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| − | A determination is made that a memory device of a memory sub-system is to be transitioned to a sleep mode. A command is initiated to cause a standby circuit associated with the memory device to enter into a low power mode while a power supply of the memory sub-system is maintained in a powered state. In the low power mode, a reference voltage is supplied to a voltage regulator of the standby circuit to supply a standby current level to the memory device during the sleep mode.
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| | ===UNBALANCED PROGRAMMED DATA STATES IN MEMORY (17712948)=== | | ===UNBALANCED PROGRAMMED DATA STATES IN MEMORY (17712948)=== |
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| | '''Inventor''' | | '''Inventor''' |
| | Christophe Laurent | | Christophe Laurent |
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| − | '''Brief explanation'''
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| − | The abstract describes a technology that deals with unbalanced programmed data states in memory. It involves a memory with a group of memory cells and circuitry that determines a specific number of memory cells in the group to be programmed to a first data state. This determined quantity can be either less than or greater than half of the total memory cells in the group. The circuitry then proceeds to program the determined quantity of memory cells to the first data state, while the remaining quantity of memory cells in the group is programmed to a second data state.
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| − | '''Abstract'''
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| − | The present disclosure includes apparatuses, methods, and systems for unbalanced programmed data states in memory. An embodiment includes a memory having a group of memory cells, and circuitry configured to determine a quantity of the memory cells of the group to program to a first data state, wherein the determined quantity of memory cells is less than or greater than half of the memory cells of the group, program the determined quantity of the memory cells of the group to the first data state, and program a remaining quantity of the memory cells of the group to a second data state.
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| | ===TECHNIQUES FOR MEMORY CELL REFRESH (17712972)=== | | ===TECHNIQUES FOR MEMORY CELL REFRESH (17712972)=== |
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| | '''Inventor''' | | '''Inventor''' |
| | Vincenzo Reina | | Vincenzo Reina |
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| − | '''Brief explanation'''
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| − | This abstract describes methods, systems, and devices for memory cell refresh techniques. It explains that a memory system can enter a low power mode where it periodically performs a refresh operation. The memory system and a host system can support a command to enter this low power mode. During this mode, the memory system receives power supply from one or more supported power supplies to remain active and continue the refresh operation. The abstract also mentions that the memory system can adjust the frequency of the refresh operation based on certain triggering events like high temperature or system age.
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| − | '''Abstract'''
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| − | Methods, systems, and devices for techniques for memory cell refresh are described. A memory system may support a low power mode in which the memory system may periodically perform a refresh operation. In some cases, the memory system and a host system coupled with the memory system may support a command to enter the low power mode. As part of the low power mode, the memory system may receive at least one power supply of one or more supported power supplies, such that the memory system may remain active and thus periodically perform the refresh operation. In some cases, the memory system may adjust the periodicity of the refresh operation in response to detecting a triggering event, such as a high temperature, a large system age, or a combination thereof.
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| | ===TECHNIQUES TO REFRESH MEMORY SYSTEMS OPERATING IN LOW POWER STATES (17713641)=== | | ===TECHNIQUES TO REFRESH MEMORY SYSTEMS OPERATING IN LOW POWER STATES (17713641)=== |
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| | '''Inventor''' | | '''Inventor''' |
| | Vincenzo Reina | | Vincenzo Reina |
| − |
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| − | '''Brief explanation'''
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| − | This abstract describes methods, systems, and devices for refreshing memory systems that operate in low power states. The memory system can be in a power mode where the power supply is deactivated. However, the memory system can still receive power during a specific time period while in this power mode. If the memory system does not receive any commands during this time period, it can perform a self-refresh operation to maintain its functionality.
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| − | '''Abstract'''
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| − | Methods, systems, and devices for techniques to refresh memory systems operating in low power states are described. The memory system may operate in a first power mode that includes deactivation of a voltage rail that supplies power to the memory system. The memory system may receive the power over the voltage rail during a time period that the memory system is operating in the first power mode. In some cases, the memory system may determine that the power may be received for a duration and a command is not received during that duration. The memory system may perform a self-refresh operation based on determining that the duration indicated by the timer expires without receiving a command.
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| | ===APPARATUSES AND METHODS FOR CONTROLLING WORD LINE DISCHARGE (17711858)=== | | ===APPARATUSES AND METHODS FOR CONTROLLING WORD LINE DISCHARGE (17711858)=== |
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| | '''Inventor''' | | '''Inventor''' |
| | Toshiyuki Sato | | Toshiyuki Sato |
| − |
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| − | '''Brief explanation'''
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| − | The abstract describes an apparatus that includes a subword driver, a word driver control circuit, and a word driver. The subword driver is responsible for driving a subword line and consists of a transistor connected to the subword line. The word driver control circuit provides a first control signal and a second control signal. The word driver receives these control signals and generates a driving signal for the subword driver. This driving signal includes a series of reset pulses that activate the transistor multiple times to discharge the subword line. Additionally, the driving signal includes a transition after the reset pulses to further discharge the subword line.
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| − | '''Abstract'''
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| − | An apparatus includes a subword driver configured to drive a subword line, wherein the subword driver includes a transistor coupled to the subword line, a word driver control circuit configured to provide a first control signal and a second control signal, and a word driver configured to receive the first and second control signals, and based on the first control signal provide a driving signal including a plurality of reset pulses to the transistor of the subword driver to activate the transistor a corresponding plurality of times to discharge the subword line, and further provide the driving signal including a transition following the plurality of reset pulses to activate the transistor to further discharge the subword line.
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| | ===APPARATUSES AND METHODS FOR ROW DECODER WITH MULTIPLE SECTION ENABLE SIGNAL VOLTAGE DOMAINS (17709753)=== | | ===APPARATUSES AND METHODS FOR ROW DECODER WITH MULTIPLE SECTION ENABLE SIGNAL VOLTAGE DOMAINS (17709753)=== |
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| | '''Inventor''' | | '''Inventor''' |
| | SANG HOON SHIN | | SANG HOON SHIN |
| − |
| |
| − | '''Brief explanation'''
| |
| − | This abstract describes a technology that allows for the decoding of a row address in a computer memory system. The row address is converted into a pre-enable signal, which is then used to generate two section enable signals. These section enable signals are in different voltage domains, with each domain representing a logical high. The pre-enable signal is in a separate voltage domain. A word line driver signal is then generated based on the section enable signals. In simpler terms, this technology helps in efficiently decoding row addresses in computer memory systems.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Apparatuses, systems, and methods for a row decoder with multiple section enable signal voltage domains. A row address is decoded into a pre-enable signal. A first section enable signal and a second section enable signal are generated based on the pre-enable signal. The first section enable signal is in a first voltage domain where a first voltage represents an logical high, the second section enable signal is in a second voltage domain where a second voltage represents a logical high, and the pre-enable signal is in a third voltage domain where a third voltage represents a logical high. The second voltage is between the first and third voltages. A word line driver signal is generated based on the first and the second section enable signals.
| |
| | | | |
| | ===ALL LEVEL COARSE/FINE PROGRAMMING OF MEMORY CELLS (18127768)=== | | ===ALL LEVEL COARSE/FINE PROGRAMMING OF MEMORY CELLS (18127768)=== |
| Line 231: |
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| | '''Inventor''' | | '''Inventor''' |
| | Lawrence Celso Miranda | | Lawrence Celso Miranda |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes systems and methods for programming memory cells at different levels of precision. It explains that a memory device consists of a memory array with multiple memory cells connected to wordlines and bitlines. The controller of the device performs various operations, including identifying a set of memory cells for programming, applying different voltages to the wordline and bitlines over specific time periods, and incrementing the voltages accordingly. The abstract does not provide any specific claims or promises, but rather presents a technical description of the memory programming process.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Described are systems and methods for all level coarse/fine programming of memory cells. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying a set of memory cells for performing a memory programming operation, wherein the memory cells are electrically coupled to a target wordline and a set of target bitlines; causing a first voltage to be applied to the target wordline, wherein the first voltage is incremented every time period over a number of time periods that corresponds to a number of threshold voltages to be programmed; causing a second voltage to be applied to a first bitline over the number of time periods; causing a third voltage to be applied to a second bitline, wherein the third voltage is incremented during a second time period of the number of time periods, wherein the second time period follows a first time period; causing a fourth voltage to be applied to a third bitline, wherein the fourth voltage is incremented during a third time period of the number of time periods, wherein the third time period follows the second time period; and causing a fifth voltage to be applied to a fourth bitline over the number of time periods.
| |
| | | | |
| | ===MEMORY DEVICES HAVING SOURCE LINES DIRECTLY COUPLED TO BODY REGIONS AND METHODS (18205679)=== | | ===MEMORY DEVICES HAVING SOURCE LINES DIRECTLY COUPLED TO BODY REGIONS AND METHODS (18205679)=== |
| Line 242: |
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| | '''Inventor''' | | '''Inventor''' |
| | Akira Goda | | Akira Goda |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes memory devices and memory cell strings, as well as methods for operating these memory devices. One specific configuration mentioned is the direct coupling of an elongated body region to a source line. This configuration aims to provide a reliable bias to the body region for memory operations like erasing. The abstract does not oversell any claims or provide a title for the described content.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing.
| |
| | | | |
| | ===TECHNIQUES FOR DETERMINING AN INTERFACE CONNECTION STATUS (17657063)=== | | ===TECHNIQUES FOR DETERMINING AN INTERFACE CONNECTION STATUS (17657063)=== |
| Line 253: |
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| | '''Inventor''' | | '''Inventor''' |
| | Melissa I. Uribe | | Melissa I. Uribe |
| − |
| |
| − | '''Brief explanation'''
| |
| − | This abstract describes methods, systems, and devices for determining the connection status of an interface between a host device and a memory device. The host device sends two sets of data in a specific pattern over different transmission lines of the interface. The memory device compares the two sets of data and based on the comparison, sends an indication of the connection status back to the host device.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Methods, systems, and devices for techniques for determining an interface connection status are described. A system may include an interface between a host device and a memory device. The host device may transmit to the memory device first data in a pattern over a first set of transmission lines of the interface. The host device may also transmit to the memory device second data in the pattern over a second set of transmission lines of the interface. The memory device may compare the first data and the second data, and based on the comparison, send an indication of a connection status of the interface to the host device.
| |
| | | | |
| | ===MEMORY DEVICE SIDEBAND SYSTEMS AND METHODS (17710601)=== | | ===MEMORY DEVICE SIDEBAND SYSTEMS AND METHODS (17710601)=== |
| Line 264: |
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| | '''Inventor''' | | '''Inventor''' |
| | Joshua E. Alzheimer | | Joshua E. Alzheimer |
| − |
| |
| − | '''Brief explanation'''
| |
| − | This abstract describes a memory device that has additional circuitry called sideband circuitry. This circuitry provides extra functionality without interfering with the normal operations of the memory device. The memory device also has sideband pins that can transmit sideband information to an external device. This sideband information can be in the form of digital or analog signals. The memory device uses a data protocol to communicate this sideband information with the external device. Additionally, the abstract mentions systems and methods for receiving sideband information from multiple memory devices in a memory system. These systems and methods aim to reduce latency and increase the functionality of the memory system that includes these memory devices.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A memory device may include sideband circuitry to provide additional functionality without interfering with normal operations of the memory device. The memory device may also include sideband pins to provide sideband information to an external device. The sideband information may include various digital or analog signals. In some cases, a sideband circuit of the memory device may use a data protocol for communicating the sideband information with the external device. Furthermore, systems and methods for receiving sideband information from multiple memory devices of a memory system are described to reduce latency and increase functionality of a memory system including such memory devices.
| |
| | | | |
| | ===Error Correction in a Memory Device having an Error Correction Code of a Predetermined Code Rate (17712550)=== | | ===Error Correction in a Memory Device having an Error Correction Code of a Predetermined Code Rate (17712550)=== |
| Line 275: |
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| | '''Inventor''' | | '''Inventor''' |
| | Mustafa N. Kaynak | | Mustafa N. Kaynak |
| − |
| |
| − | '''Brief explanation'''
| |
| − | This abstract describes an apparatus that uses memory cells and an error correction module to improve the recovery from random bit errors in raw data retrieved from the memory cells. The apparatus stores both user data and redundant data in the memory cells, with the redundant data generated from both the user data and known data. By doing this, the error correction module is able to better recover from random bit errors in the raw data. This increased capability can help extend the lifespan of the memory cells and improve the reliability of retrieving error-free data from them.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | An apparatus having memory cells, an error correction module with a predetermined code rate, a processing device configured to arrange data storage in the memory cells for improved capability in recovering from random bit errors in raw data retrieved from the memory cells. For example, user data and redundant data are stored in the memory cells. The redundant data is generated according to the predetermined code rate from not only the user data but also known data. The known data is not stored in the memory cells. As a result, the error correction module has increased capability in recovering from random bit errors in raw data retrieved from the memory cells. The increased capability can be used to extend the useful life of the memory cells and/or improve the reliability of retrieving error free data from the memory cells.
| |
| | | | |
| | ===SEMICONDUCTOR ASSEMBLIES WITH SYSTEM AND METHOD FOR SMOOTHING SURFACES OF 3D STRUCTURES (18111496)=== | | ===SEMICONDUCTOR ASSEMBLIES WITH SYSTEM AND METHOD FOR SMOOTHING SURFACES OF 3D STRUCTURES (18111496)=== |
| Line 286: |
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| | '''Inventor''' | | '''Inventor''' |
| | Andrew M. Bayless | | Andrew M. Bayless |
| − |
| |
| − | '''Brief explanation'''
| |
| − | This abstract describes a method for smoothing structures made of curable materials on a semiconductor device. The process involves applying a layer of photo-responsive material on a substrate and exposing it to ultraviolet light through a grayscale gradient mask. Unwanted portions of the material are then removed, and the remaining material is cured. The curing process involves increasing the temperature gradually, maintaining it at a certain level, and then decreasing it to a predetermined finish temperature.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A method for smoothing structures formed of curable materials on a semiconductor device includes applying a layer of photo-responsive material on a substrate. The photo-responsive material is exposed to ultraviolet light through a grayscale gradient mask. Subsequent to removing unwanted portions of the photo-responsive material, the photo-responsive material that remains on the substrate is cured. During the curing process, the temperature is increased from a starting temperature to a final cure temperature over a first time period that allows the photo-responsive material to cross-flow. The temperature of the photo-responsive material is maintained at approximately the final cure temperature for a second time period, and then the temperature of the photo-responsive material is decreased to a predetermined finish temperature over a third time period.
| |
| | | | |
| | ===METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED ELECTRONIC SYSTEMS (18333235)=== | | ===METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED ELECTRONIC SYSTEMS (18333235)=== |
| Line 297: |
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| | '''Inventor''' | | '''Inventor''' |
| | Kunal R. Parekh | | Kunal R. Parekh |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a method of creating a microelectronic device. It involves forming line structures made of conductive and insulative materials, with trenches separating them. An isolation material is then applied to the surfaces of the line structures, both inside and outside the trenches, creating air gaps between the line structures. Openings are made through the isolation material to expose the insulative material of the line structures, which is then removed to reach the conductive material. Conductive contact structures and pad structures are then formed. The abstract also mentions that there are additional methods, microelectronic devices, memory devices, and electronic systems described in the document.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A method of forming a microelectronic device comprises forming line structures comprising conductive material and insulative material overlying the conductive material, the line structures separated from one another by trenches. An isolation material is formed on surfaces of the line structures inside and outside of the trenches, the isolation material only partially filling the trenches to form air gaps interposed between the line structures. Openings are formed to extend through the isolation material and expose portions of the insulative material of the line structures. The exposed portions of the insulative material of the line structures are removed to form extended openings extending to the conductive material of the line structures. Conductive contact structures are formed within the extended openings. Conductive pad structures are formed on the conductive contact structures. Additional methods, microelectronic devices, memory devices, and electronic systems are also described.
| |
| | | | |
| | ===MICROELECTRONIC DEVICES WITH STAIRCASED STADIUMS AND BOTH THROUGH-STEP AND TO-STEP CONTACTS, AND RELATED SYSTEMS AND METHODS (17709020)=== | | ===MICROELECTRONIC DEVICES WITH STAIRCASED STADIUMS AND BOTH THROUGH-STEP AND TO-STEP CONTACTS, AND RELATED SYSTEMS AND METHODS (17709020)=== |
| Line 308: |
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| | '''Inventor''' | | '''Inventor''' |
| | Harsh Narendrakumar Jain | | Harsh Narendrakumar Jain |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a type of microelectronic device that consists of a stacked structure with alternating layers of insulative and conductive materials. Within this structure, there is a stadium-like shape with steps located at the ends of some of the layers. These steps are made of the upper surface of the conductive materials. The device also includes conductive contact structures that connect to these steps. These contact structures have two parts - one that terminates at the surface of the step and another that extends through the step. The abstract also mentions that there are related fabrication methods and electronic systems discussed in the document.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Microelectronic devices include a tiered stack comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A stadium within the tiered stack includes a staircase with steps at ends of some of the tiers. The steps each have a tread provided by an upper surface portion of one of the conductive structures. Conductive contact structures extend to one of the steps and include a first conductive contact structure terminating at the tread of the step and a second conductive contact structure extending through the tread of the step. Related fabrication methods and electronic systems are also disclosed.
| |
| | | | |
| | ===MICROELECTRONIC DEVICES WITH DIFFERENT STAIRCASED STADIUMS HAVING CONSISTENT MULTI-TIER STEP RISER HEIGHT, AND RELATED SYSTEMS AND METHODS (17657264)=== | | ===MICROELECTRONIC DEVICES WITH DIFFERENT STAIRCASED STADIUMS HAVING CONSISTENT MULTI-TIER STEP RISER HEIGHT, AND RELATED SYSTEMS AND METHODS (17657264)=== |
| Line 319: |
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| | '''Inventor''' | | '''Inventor''' |
| | Lifang Xu | | Lifang Xu |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a type of microelectronic device that has a stack structure made up of insulative and conductive layers arranged in tiers. Within this structure, there are different stadiums, each with a different number of staircase sets. Some stadiums have multiple parallel sets of staircases, while others have only one set. The staircases are made up of steps located at the ends of the conductive structures, all with the same height. The fabrication process involves creating an opening for each stadium, regardless of the number of staircase sets, and ensuring that all steps have the same height. The abstract also mentions that electronic systems using these devices are also discussed.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Microelectronic devices include a stack structure having a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of stadiums, within the stack structure, includes stadiums of differing numbers of staircase sets, such as a stadium having multiple parallel sets of staircases and an additional stadium having a single set of staircases. Each of the staircases comprises steps, at ends of the conductive structures, with a same multi-tier riser height. In methods of fabrication, a same initial stadium opening may be concurrently formed for each of the stadiums—regardless of whether the stadium is to include the single set or the multiple parallel sets of staircases—with the steps of the same multi-tier riser height. Electronic systems are also disclosed.
| |
| | | | |
| | ===ANTIMONY-GALLIUM-ZINC-OXIDE MATERIALS (17712294)=== | | ===ANTIMONY-GALLIUM-ZINC-OXIDE MATERIALS (17712294)=== |
| Line 330: |
Line 145: |
| | '''Inventor''' | | '''Inventor''' |
| | Adharsh Rajagopal | | Adharsh Rajagopal |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a technology related to transistors. These transistors have three main regions: a first source/drain region, a second source/drain region, and a channel region. The channel region is made up of a material called antimony-gallium-zinc-oxide (SbGZO). The abstract does not provide any further details about the specific systems, methods, or apparatus related to this technology.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Systems, methods and apparatus are provided for transistors having a first source/drain region, a second source/drain region, and a channel region, wherein the channel region comprises an antimony-gallium-zinc-oxide (SbGZO) material.
| |
| | | | |
| | ===Memory Circuitry Comprising Strings Of Memory Cells (17712776)=== | | ===Memory Circuitry Comprising Strings Of Memory Cells (17712776)=== |
| Line 341: |
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| | '''Inventor''' | | '''Inventor''' |
| | Dhirendra Dhananjay Vaidya | | Dhirendra Dhananjay Vaidya |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a memory circuitry that consists of memory cells arranged in strings. These memory cells are organized into memory blocks, which are stacked vertically and consist of alternating insulative and conductive tiers. The memory blocks are laterally spaced and are located above a conductor tier. The memory cells in the memory-array region are connected to the conductor tier through operative channel-material strings that pass through the insulative and conductive tiers. The memory blocks also have an intermediate region between the operative channel-material strings and a stair-step region. In this intermediate region, there is a dummy through-array-via (TAV) that passes through the insulative and conductive tiers and is directly connected to the operative channel-material strings. The purpose of this dummy TAV is not specified in the abstract.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Memory circuitry comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. The insulative tiers and the conductive tiers of the laterally-spaced memory blocks extend from a memory-array region into a stair-step region. Strings of memory cells comprise operative channel-material strings that extend through the insulative tiers and the conductive tiers in individual of the laterally-spaced memory blocks in the memory-array region. The operative channel-material strings directly electrically couple with conductor material of the conductor tier. The individual laterally-spaced memory blocks comprise an intermediate region between the operative channel-material strings and the stair-step region. A dummy through-array-via (TAV) extends through the insulative tiers and the conductive tiers in the intermediate region in the individual laterally-spaced memory blocks. The dummy TAV is directly electrically coupled with the operative channel-material strings in its memory block. Other embodiments are disclosed.
| |
| | | | |
| | ===APPARATUSES INCLUDING LOW-K SPACERS AND METHODS FOR FORMING SAME (17711909)=== | | ===APPARATUSES INCLUDING LOW-K SPACERS AND METHODS FOR FORMING SAME (17711909)=== |
| Line 352: |
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| | '''Inventor''' | | '''Inventor''' |
| | Kehan Zhang | | Kehan Zhang |
| − |
| |
| − | '''Brief explanation'''
| |
| − | This abstract describes a semiconductor structure that consists of two device structures on a substrate. Each device structure has sidewall spacers, which are layers placed on the sides of the structures. The first sidewall spacer includes a liner layer, an oxide spacer, and an etch stop layer. The second sidewall spacer includes a liner layer, an inner oxide spacer, an etch stop layer, and an outer oxide spacer.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A semiconductor structure includes a first sidewall spacer on sidewalls of a first device structure on a surface of a substrate and a second sidewall spacer on sidewalls of a second device structure on the surface of the substrate. The first sidewall spacer includes a first liner layer on sidewalls of the first device structure, a first oxide spacer on the first liner layer and on the surface of the substrate, and a first etch stop layer on the first oxide spacer. The second sidewall spacer includes a second liner layer on sidewalls of the second device structure, an inner oxide spacer on the second liner layer and on the surface of the substrate, a second etch stop layer on the inner oxide layer, and an outer oxide spacer on the second etch stop layer.
| |
| | | | |
| | ===LOW POWER VB CLASS AB AMPLIFIER WITH LOCAL COMMON MODE FEEDBACK (17711183)=== | | ===LOW POWER VB CLASS AB AMPLIFIER WITH LOCAL COMMON MODE FEEDBACK (17711183)=== |
| Line 363: |
Line 160: |
| | '''Inventor''' | | '''Inventor''' |
| | Zhi Qi Huang | | Zhi Qi Huang |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes an amplifier that consists of two stages. The first stage has a floating current source that helps maintain the current within a certain range. It also has a local common mode feedback that amplifies the input signal. The second stage includes a driver that supplies a load current to a load connected to the amplifier.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | An amplifier includes a first stage and a second stage. The first stage includes a floating current source to maintain current within a threshold. The first stage also includes a local common mode feedback configured to provide gain to an input signal. Moreover, the second stage includes a driver that provides a load current to a load coupled to the amplifier.
| |
| | | | |
| | ===SEMICONDUCTOR DEVICE (17711972)=== | | ===SEMICONDUCTOR DEVICE (17711972)=== |
| Line 374: |
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| | '''Inventor''' | | '''Inventor''' |
| | Mitsunari Sukekawa | | Mitsunari Sukekawa |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes an apparatus that includes a memory mat with multiple vertical memory cell transistors. The memory mat is covered by a shield structure, which surrounds each of the vertical memory cell transistors. Above the shield structure, there is a ring-shaped wiring that is connected to the shield structure at the edge region.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | An apparatus includes: a memory mat including a plurality of vertical memory cell transistors; a shield structure covering the memory mat and surrounding each of the plurality of vertical memory cell transistors; and a ring-shaped wiring above the shield structure, the ring-shaped wiring being connected to the shield structure in an edge region of the shield structure.
| |
| | | | |
| | ===Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells (17710262)=== | | ===Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells (17710262)=== |
| Line 385: |
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| | '''Inventor''' | | '''Inventor''' |
| | Shyam Surthi | | Shyam Surthi |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a memory array made up of strings of memory cells. These memory cells are arranged in a vertical stack, with alternating layers of insulative and conductive tiers. The memory cells are connected to a conductor tier, and the channel material of the memory cells directly connects with the conductor material. The memory-cell region of the stack contains memory cells, with the insulative tiers on the sides of the memory-cell strings mostly consisting of empty space. Above the memory-cell region is an upper region, which contains additional conductive tiers and select gates. The insulative tiers in this upper region are mostly solid. The abstract also mentions that there are other embodiments and methods discussed.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A memory array comprising strings of memory cells comprises a vertical stack comprising vertically-alternating insulative tiers and conductive tiers directly above a conductor tier. Channel-material-string constructions of memory-cell strings extend through the insulative and conductive tiers. The channel material of the channel-material-string constructions directly electrically couples with conductor material of the conductor tier. The vertical stack comprising a memory-cell region comprises memory cells. Individual of the insulative tiers in the memory-cell region laterally-outward of the channel-material-string constructions have at least a majority of their insulative matter being void space. The vertical stack comprises an upper region directly above the memory-cell region. The upper region comprises at least two of the conductive tiers and that comprise upper select gates Individual of the insulative tiers in the upper region laterally-outward of the channel-material-string constructions have at least a majority of their insulative matter being solid. Other embodiments, including method, are disclosed.
| |
| | | | |
| | ===NAND PILLAR MEMORY DEVICE AND METHOD (17711620)=== | | ===NAND PILLAR MEMORY DEVICE AND METHOD (17711620)=== |
| Line 396: |
Line 175: |
| | '''Inventor''' | | '''Inventor''' |
| | Gianpietro Carnevale | | Gianpietro Carnevale |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes the invention of memory devices and systems. These devices and systems include memory strings that have a conductor channel shell and a low dielectric constant central region. In one example, the memory strings have a conductor channel shell and a hollow central region.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include memory strings with a conductor channel shell and a low dielectric constant central region. In one example, memory devices, systems and methods include memory strings with a conductor channel shell and a hollow central region.
| |
| | | | |
| | ===Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells (17713913)=== | | ===Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells (17713913)=== |
| Line 407: |
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| | '''Inventor''' | | '''Inventor''' |
| | Collin Howder | | Collin Howder |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a memory array that consists of strings of memory cells. These memory cells are organized into memory blocks, which are stacked vertically and separated by insulative and conductive tiers. Each memory cell has a construction called a channel-material-string, which includes a charge-blocking-material string, a storage-material string, a charge-passage-material string, and a channel-material string. The charge-blocking-material string is located below the insulative tiers and above the lowest conductive tier. The channel material of each channel-material string is electrically connected to the conductor material of the conductor tier. The abstract does not provide any specific methods or processes, but rather focuses on the structure of the memory array.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A memory array comprising strings of memory cells comprises laterally-spaced memory-blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above conductor material of a conductor tier. Channel-material-string constructions extend through the insulative and conductive tiers to a lowest of the conductive tiers. The channel-material-string constructions individually comprise a charge-blocking-material string, a storage-material string laterally-inward of the charge-blocking-material string, a charge-passage-material string laterally-inward of the storage-material string, and a channel-material string laterally-inward of the charge-passage-material string. A lowest surface of the charge-blocking-material string that is above a lowest surface of the lowest conductive tier is below a lowest surface of a lowest of the insulative tiers that is immediately-above the lowest conductive tier. Conductive material in the lowest conductive tier directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Structure independent of method is disclosed.
| |
| | | | |
| | ===Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells (17713955)=== | | ===Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells (17713955)=== |
| Line 418: |
Line 185: |
| | '''Inventor''' | | '''Inventor''' |
| | Collin Howder | | Collin Howder |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a memory array that consists of strings of memory cells. These memory cells are organized into memory blocks, which are stacked vertically and separated by insulative and conductive tiers. Each memory cell has a construction called a channel-material-string, which includes a charge-blocking-material string, a storage-material string, a charge-passage-material string, and a channel-material string. The channel material of each channel-material string is electrically connected to the conductor material of the conductor tier through conductive material in the lowest conductive tier. This conductive material is located next to the inner sidewall of the charge-blocking-material string. The abstract also mentions that methods for implementing this memory array are disclosed.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above conductor material of a conductor tier. Channel-material-string constructions extend through the insulative and conductive tiers to a lowest of the conductive tiers. The channel-material-string constructions individually comprise a charge-blocking-material string, a storage-material string laterally-inward of the charge-blocking-material string, a charge-passage-material string laterally-inward of the storage-material string, and a channel-material string laterally-inward of the charge-passage-material string. Conductive material in the lowest conductive tier directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. The conductive material is laterally-aside and laterally-inward of a laterally-inner sidewall of the charge-blocking-material string. Methods are disclosed.
| |
