View source for MEMORY CONTROLLER PERFORMING SELECTIVE AND PARALLEL ERROR CORRECTION, SYSTEM INCLUDING THE SAME AND OPERATING METHOD OF MEMORY DEVICE: abstract simplified (18335375)

*This abstract for appeared for patent application  number 18335375 Titled 'MEMORY CONTROLLER PERFORMING SELECTIVE AND PARALLEL ERROR CORRECTION, SYSTEM INCLUDING THE SAME AND OPERATING METHOD OF MEMORY DEVICE'

==Simplified Explanation==

This abstract describes a memory controller that is designed to manage the memory accessed by a device connected to a host processor through a bus. The memory controller has two interface circuits, one to communicate with the host processor and the other to communicate with the memory. It also includes an error detection circuit that can identify errors in data received from the memory in response to a read request from the host processor. The memory controller has a variable error correction circuit that can correct the detected errors based on a reference latency and a reference error correction level provided in an error correction option. Additionally, there is a fixed error correction circuit that can correct errors simultaneously with the variable error correction circuit.


==Original Abstract Submitted==

A memory controller is provided that is configured to control a memory accessed by a device connected to a host processor via a bus. The memory controller is configured to control a memory accessed by a device connected to a host processor via a bus, and includes a first interface circuit configured to communicate with the host processor; a second interface circuit configured to communicate with the memory; an error detection circuit configured to detect an error present in data received from the second interface circuit in response to a first read request received from the first interface circuit; a variable error correction circuit configured to correct the error based on at least one of a reference latency and a reference error correction level included in a first error correction option; and a fixed error correction circuit configured to correct the error in parallel with an operation of the variable error correction circuit.