Kioxia corporation (20240096419). SEMICONDUCTOR MEMORY DEVICE simplified abstract

SEMICONDUCTOR MEMORY DEVICE

Organization Name

kioxia corporation

Inventor(s)

Hiroshi Maejima of Setagaya Tokyo (JP)

SEMICONDUCTOR MEMORY DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240096419 titled 'SEMICONDUCTOR MEMORY DEVICE

Simplified Explanation

The semiconductor memory device described in the abstract utilizes different voltages applied to the selection gate lines during a read operation to improve performance and efficiency.

• Memory cell array with memory strings
• First and second selection transistors
• Controller applies different voltages during read operation
• First voltage higher than ground to source line
• Second voltage to selected memory string
• Second voltage also applied to first selection gate lines of non-selected memory strings during first period
• Third voltage higher than ground and lower than second voltage applied to first selection gate lines of non-selected memory strings during second period

Potential Applications

The technology described in this patent application could be applied in various semiconductor memory devices, such as flash memory, solid-state drives, and other storage devices.

Problems Solved

This technology helps improve the efficiency and performance of semiconductor memory devices during read operations by optimizing the voltages applied to the memory strings.

Benefits

- Enhanced read operation performance - Improved efficiency in semiconductor memory devices - Potential for faster data access and retrieval

Potential Commercial Applications

The innovative voltage application technique described in this patent application could be utilized in the development of next-generation semiconductor memory devices for consumer electronics, data centers, and other applications.

Possible Prior Art

One possible prior art for this technology could be the use of different voltage levels in memory devices to optimize read operations. However, the specific technique described in this patent application may be novel and inventive in its approach.

How does this technology compare to existing voltage optimization techniques in semiconductor memory devices?

The article does not provide a direct comparison between this technology and existing voltage optimization techniques in semiconductor memory devices. Further research or analysis would be needed to determine the specific advantages and differences of this approach.

What impact could this technology have on the overall performance and efficiency of semiconductor memory devices?

While the benefits of this technology are mentioned in the article, the specific impact on the overall performance and efficiency of semiconductor memory devices is not fully explored. Additional studies or experiments may be required to quantify the potential improvements brought by this innovation.

Original Abstract Submitted

a semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. during a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. the second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. a third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.