|
|
| Line 1: |
Line 1: |
| − | '''Summary of the patent applications from Kioxia Corporation on October 5th, 2023'''
| |
| − |
| |
| − | Kioxia Corporation has recently filed several patents related to semiconductor storage devices and memory systems. These patents involve various aspects such as the structure of the storage devices, memory cell arrays, control circuits, and lithography processes. Some notable applications of these patents include:
| |
| − |
| |
| − | * A semiconductor storage device consisting of multiple layers of conductive material on a substrate, with a pillar containing a semiconductor layer. The pillar intersects with the conductive layers to act as memory cells.
| |
| − | * A semiconductor memory device with stacked layers, including a gate electrode layer, insulating layers, and a semiconductor layer. A specific layer contains silicon and nitrogen, with different regions having varying concentrations of fluorine.
| |
| − | * A memory system with a semiconductor memory and a controller. The controller instructs the semiconductor memory to perform operations on selected blocks, applying voltage to memory cells. The number of blocks to which voltage is applied per unit time is greater in the second operation compared to the first operation.
| |
| − | * A circuit for calculating syndromes in a composite field, using matrix product calculations and arithmetic matrices.
| |
| − | * A semiconductor storage device consisting of two chips bonded together, with conductive layers, a semiconductor pillar, and power supply electrodes on the first chip, and a semiconductor substrate and transistors on the second chip.
| |
| − | * A semiconductor device with a substrate, transistor, insulating layer, and a sealing portion. The sealing portion encircles the outer periphery of a region within the substrate and contains a void.
| |
| − | * A plate for imprint lithography, with a patterned portion having a recessed groove and a columnar portion extending beyond the surface.
| |
| − | * A semiconductor memory device with a memory cell array, word line, bit lines, sense amplifier, and controller. It performs write operations using multiple program loops, applying different voltages to bit lines and a program voltage to the word line.
| |
| − | * A semiconductor storage device with multiple strings of memory cell transistors, word lines, bit lines, a source line, and a control circuit. The control circuit performs erase operations on the memory cell transistors using different erase-verify operations for open and closed blocks.
| |
| − | * A semiconductor memory device with a first pad for connection, a clock generation circuit, an output circuit, a designation circuit for selecting time slots, and a peak control circuit for generating a current peak at a specific timing.
| |
| − |
| |
| − | Overall, Kioxia Corporation has been actively filing patents related to various aspects of semiconductor storage devices and memory systems, showcasing their commitment to innovation in the field.
| |
| − |
| |
| − |
| |
| − |
| |
| − |
| |
| | ==Patent applications for Kioxia Corporation on October 5th, 2023== | | ==Patent applications for Kioxia Corporation on October 5th, 2023== |
| | | | |
| Line 25: |
Line 5: |
| | '''Inventor''' | | '''Inventor''' |
| | Kazufumi NOMURA | | Kazufumi NOMURA |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a production apparatus that is used to cut a first surface of an object using a rotating grindstone. The apparatus includes a rotating body that spins the grindstone, a holding unit that touches a second surface of the object, and a displacement unit that moves at least a part of the second surface in the same direction as the rotation axis of the rotating body.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A production apparatus includes: a rotating body configured to rotate a grindstone to cut a first surface of an object; a holding unit configured to contact a second surface of the object; and a displacement unit configured to displace at least a portion of the second surface of the object in a rotation axis direction of the rotating body.
| |
| | | | |
| | ===SEMICONDUCTOR STORAGE DEVICE (17806815)=== | | ===SEMICONDUCTOR STORAGE DEVICE (17806815)=== |
| Line 36: |
Line 10: |
| | '''Inventor''' | | '''Inventor''' |
| | Ryuji NISHIKUBO | | Ryuji NISHIKUBO |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a semiconductor storage device that consists of different types of memory chips. It includes a volatile memory, which is temporary storage, and nonvolatile memory chips, which retain data even when power is turned off. The device also has channels, which connect the nonvolatile memory chips, and nonvolatile memory interfaces, which control the chips through the channels. Additionally, there is a bus arbiter that manages the use of a bus, which is used to transfer data between the volatile memory and the nonvolatile memory chips. The bus arbiter adjusts the data transfer based on the bandwidth capacity of the bus.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | According to one embodiment, a semiconductor storage device includes a volatile memory, nonvolatile memory chips, channels, nonvolatile memory interfaces, and a bus arbiter. Each of the channels is connected to at least one nonvolatile memory chip of the nonvolatile memory chips. Each of the nonvolatile memory interfaces is connected to at least one channel of the channels and controls the at least one nonvolatile memory chip via the connected channel. The bus arbiter controls use of a bus in data transfer between the volatile memory and each of the nonvolatile memory chips in accordance with a bandwidth of the bus.
| |
| | | | |
| | ===MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY (18329446)=== | | ===MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY (18329446)=== |
| Line 47: |
Line 15: |
| | '''Inventor''' | | '''Inventor''' |
| | Hideki Yoshida | | Hideki Yoshida |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a memory system that receives a request to write data from a host. The system determines where to write the data in a specific block and updates a table that keeps track of the mapping between logical addresses and physical addresses within the block. It then maps the physical address of the written data to the logical address provided by the host.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | According to one embodiment, when receiving a write request to designate a first block number and a first logical address from a host, a memory system determines a first location in a first block having the first block number, to which data from the host is to be written, and writes the data from the host to the first location of the first block. The memory system updates a first address translation table managing mapping between logical addresses and in-block physical addresses of the first block, and maps a first in-block physical address indicative of the first location to the first logical address.
| |
| | | | |
| | ===MEMORY SYSTEM AND CONTROL METHOD (18114538)=== | | ===MEMORY SYSTEM AND CONTROL METHOD (18114538)=== |
| Line 58: |
Line 20: |
| | '''Inventor''' | | '''Inventor''' |
| | Tetsuya YASUDA | | Tetsuya YASUDA |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a memory system that includes a non-volatile memory and a controller. The memory system has multiple physical blocks, and the controller is responsible for allocating these blocks into different sets. The controller also groups these sets based on the number of defective blocks in each set. Finally, the controller selects multiple sets from different groups to create a new set.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | According to one embodiment, a memory system includes a non-volatile memory including a plurality of physical blocks and a controller. The controller is configured to allocate the plurality of physical blocks to a plurality of first block sets each including physical blocks among the plurality of physical blocks, generate a plurality of groups obtained by grouping the plurality of first block sets by the number of defective physical blocks included in each of the plurality of first block sets, and select a plurality of the first block sets from at least two groups of the plurality of groups to generate a second block set from the plurality of selected first block sets.
| |
| | | | |
| | ===MEMORY SYSTEM AND METHOD (17899426)=== | | ===MEMORY SYSTEM AND METHOD (17899426)=== |
| Line 69: |
Line 25: |
| | '''Inventor''' | | '''Inventor''' |
| | Kenji TAKAHASHI | | Kenji TAKAHASHI |
| − |
| |
| − | '''Brief explanation'''
| |
| − | This abstract describes a memory system that includes two memory cell units and a controller. The controller is able to store the time it takes to perform write and erase operations on the first memory cell unit. When the memory system is powered on, the controller receives information about the power-on time. Using this information, the controller calculates the time period since the last write or erase operation on the first memory cell unit. Based on this time period, the controller determines how long it will take to transfer data from the first memory cell unit to the second memory cell unit during a refresh operation. The controller then initiates the refresh operation at the calculated time.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A memory system includes a non-volatile memory including a first memory cell unit and a second memory cell unit, and a controller connectable to a host. The controller is configured to store an execution time of write and erase operations with respect to the first memory cell unit, receive from the host power-on time information indicating a power-on time of the memory system when the memory system is powered on, determine a first time period from a last write or erase operation with respect to the first memory cell unit based on the stored execution time and the power-on time, determine an execution time of a refresh operation of transferring data stored in the first memory cell unit to the second memory cell unit based on the first time period, and start the refresh operation at the determined execution time.
| |
| | | | |
| | ===MEMORY SYSTEM AND CONTROL METHOD (18312978)=== | | ===MEMORY SYSTEM AND CONTROL METHOD (18312978)=== |
| Line 80: |
Line 30: |
| | '''Inventor''' | | '''Inventor''' |
| | Shinichi KANNO | | Shinichi KANNO |
| − |
| |
| − | '''Brief explanation'''
| |
| − | This abstract describes a memory system that can be connected to a host device. The memory system consists of a nonvolatile memory and a controller. The nonvolatile memory is divided into multiple blocks. The controller is responsible for managing the nonvolatile memory.
| |
| − |
| |
| − | In a specific scenario, when the host sends a command to change the state of a specific block to a real locatable state, but there is another command related to reading data from that block that is either currently being executed or is yet to be executed, the controller waits until the second command is finished before changing the state of the block to the desired state.
| |
| − |
| |
| − | In simpler terms, this memory system ensures that if there is a command to change the state of a block and there is another command involving reading data from that block, the change in state will only occur after the reading command is completed.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | According to one embodiment, a memory system is connectable to a host. The memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a plurality of blocks. The controller is electrically coupled to the nonvolatile memory. The controller controls the nonvolatile memory. When receiving, from the host, a first command for changing a state of an allocated block to a real locatable state in a case where a second command that is yet to be executed or being executed involving read of data from the allocated block has been received from the host, the controller changes the state of the allocated block to the real locatable state after the second command is finished.
| |
| | | | |
| | ===SEMICONDUCTOR MEMORY DEVICE (18331804)=== | | ===SEMICONDUCTOR MEMORY DEVICE (18331804)=== |
| Line 95: |
Line 35: |
| | '''Inventor''' | | '''Inventor''' |
| | Akio SUGAHARA | | Akio SUGAHARA |
| − |
| |
| − | '''Brief explanation'''
| |
| − | This abstract describes a semiconductor memory device that has two planes of memory cells. The control circuit of the device is designed to perform write operations to store two bits per memory cell. It also performs read operations using different read voltages to read the stored bits.
| |
| − |
| |
| − | In response to a specific instruction, the control circuit reads the first bits from the first plane and the second bits from the second plane. In response to another instruction, it reads the second bits from the first plane and the first bits from the second plane.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A semiconductor memory device includes first and second planes of memory cells, and a control circuit configured to perform a write operation on the memory cells to store first and second bits per memory cell, and to perform a first read operation using a first read voltage to read the first bits and a second read operation using second and third read voltages to read the second bits. In response to a first instruction, the control circuit performs the first and second read operations to read the first bits from the first plane and the second bits from the second plane, respectively. In response to a second read instruction, the control circuit performs the second and first read operations to read the second bits from the first plane and the first bits from the second plane, respectively.
| |
| | | | |
| | ===MAINTAINING QUALIY OF SERVICE OF NON-VOLATILE MEMORY DEVICES IN HETEROGENEOUS ENVIRONMENT (17706975)=== | | ===MAINTAINING QUALIY OF SERVICE OF NON-VOLATILE MEMORY DEVICES IN HETEROGENEOUS ENVIRONMENT (17706975)=== |
| Line 108: |
Line 40: |
| | '''Inventor''' | | '''Inventor''' |
| | Yaron Klein | | Yaron Klein |
| − |
| |
| − | '''Brief explanation'''
| |
| − | This abstract describes a system where a manager of a storage system uses non-volatile memory from storage devices to create an abstracted memory structure for a user. This structure includes virtual devices and domains that correspond to the user's applications and volumes. The system determines mappings between these virtual devices and domains, and the hardware storage units in the non-volatile memory.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | In some arrangements, a manager of a storage system determines at least one abstracted memory structure for a tenant using a non-volatile memory of at least one non-volatile storage device. The abstracted memory structure includes at least one hardware storage unit of the non-volatile memory of the at least one non-volatile storage device. The at least one abstracted memory structure includes one or more of at least one virtual device corresponding to an application of the tenant or at least one domain corresponding to a volume of the application of the tenant. A virtual device mapping that maps the application of the tenant to the at least one hardware storage unit corresponding to the at least one virtual device is determined. A domain mapping that maps the volume to the at least one hardware storage unit corresponding to the at least one domain is determined.
| |
| | | | |
| | ===RECOVERY FROM BROKEN MODE (17709046)=== | | ===RECOVERY FROM BROKEN MODE (17709046)=== |
| Line 119: |
Line 45: |
| | '''Inventor''' | | '''Inventor''' |
| | Kentaro SUGINO | | Kentaro SUGINO |
| − |
| |
| − | '''Brief explanation'''
| |
| − | This abstract describes a method for recovering a storage device from a failure mode. The method involves executing a boot up process for the storage device and then checking if there is an instruction for a pseudo boot up. If such an instruction is received, the storage device switches to a pseudo boot up process. During this process, the storage device is restored to its previous operational state, up to the point where it encountered a failure triggering event that caused it to enter the failure mode. Once the pseudo boot up is complete, the storage device resumes normal operation.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A method of recovering a storage device from a failure mode by a controller, the method comprising executing a boot up of the storage device, determining whether an instruction for pseudo boot up of the storage device has been received, switching from the boot up to a pseudo boot up of the storage device if an instruction for the pseudo boot up has been received, and resuming operation of the storage device from the prior operational state. The pseudo boot up restores the storage device to a prior operational state up to the point in time when the storage device encountered a failure triggering event that caused the storage device to enter the failure mode.
| |
| | | | |
| | ===STORAGE DATA DELETION MANAGEMENT SYSTEM AND APPARATUS (17707736)=== | | ===STORAGE DATA DELETION MANAGEMENT SYSTEM AND APPARATUS (17707736)=== |
| Line 130: |
Line 50: |
| | '''Inventor''' | | '''Inventor''' |
| | Kazusa TOMONAGA | | Kazusa TOMONAGA |
| − |
| |
| − | '''Brief explanation'''
| |
| − | This abstract describes a method for sanitizing a media device, such as a hard drive or solid-state drive. The method involves using a controller to erase both the data area and internal area of the storage device. The controller then verifies that these areas have been successfully erased. Afterward, a certificate of media sanitization (CoS) is generated and registered in a distributed ledger or database. The storage device is designed to store data from an external source only in the data area, while the internal area is used for operational data necessary for the device's functioning.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A method of sanitizing a media comprising a controller and a storage device, the method comprising executing, by the controller, a command to erase a data area and an internal area of the storage device, verifying, by the controller, that at least a portion of the data area and at least a portion of the internal area of the storage device has been erased, generating, by the server, a certificate of media sanitization (CoS) of the media, and registering, by the server, an entry representative of the CoS of the media in a distributed ledger or database. Here the storage device is configured to store data received from a host external to the storage device only in the data area, and the storage device is configured to store operational data in the internal area for the operation of the storage device.
| |
| | | | |
| | ===NONVOLATILE MEMORY (17929439)=== | | ===NONVOLATILE MEMORY (17929439)=== |
| Line 141: |
Line 55: |
| | '''Inventor''' | | '''Inventor''' |
| | Yasuhiko KUROSAWA | | Yasuhiko KUROSAWA |
| − |
| |
| − | '''Brief explanation'''
| |
| − | This abstract describes a memory device that performs two programming operations. In the first operation, the threshold voltage of certain memory cells in two different sections is set. In the second operation, the threshold voltage of the same memory cells in another section is set based on temperature information. The second section has the same voltage range as the first section, while the third section has a higher voltage range.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A memory device includes control circuitry that executes a first programming operation and executes a second programming operation after the first programming operation. The first programming operation includes setting a threshold voltage of each of a second set of memory cells in a second section corresponding to write data, and setting a threshold voltage of each of the third set of memory cells in a third section. The second programming operation includes setting the threshold voltage of each of the second set of memory cells in a fifth section corresponding to the write data, and setting the threshold voltage of each of the third set of memory cells in a sixth section or a seventh section among a plurality of fourth sections in accordance with temperature information. The sixth section includes the same voltage range as the third section. The seventh section is higher in voltage than the third section.
| |
| | | | |
| | ===MEMORY DEVICE (17943432)=== | | ===MEMORY DEVICE (17943432)=== |
| Line 152: |
Line 60: |
| | '''Inventor''' | | '''Inventor''' |
| | Ryousuke TAKIZAWA | | Ryousuke TAKIZAWA |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a memory cell that has a switching element. This switching element can change from an ON state to an OFF state when the voltage applied to it decreases. There is also a read circuit that can make the second interconnect (a connection within the memory cell) in a floating state.
| |
| − |
| |
| − | After putting the second interconnect in a floating state, the read circuit compares the voltage of the second interconnect at the time when the switching element turns OFF with a second voltage. Based on this comparison, the read circuit can either apply a third voltage to the second interconnect and then put it in a floating state again, or it can apply a fourth voltage (which is lower than the third voltage) to the second interconnect without applying the third voltage.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A first switching element in a memory cell is configured to transition from an ON state to an OFF state in response to a voltage applied between its two terminals being decreased. A read circuit is configured to place the second interconnect in a floating state, and, after placing the second interconnect in the floating state and based on a comparison between a first voltage of the second interconnect at a time point of the first switching element becoming the OFF state and a second voltage, either apply a third voltage to the second interconnect and then place the second interconnect in the floating state, or apply a fourth voltage lower than the third voltage to the second interconnect without applying the third voltage to the second interconnect.
| |
| | | | |
| | ===SEMICONDUCTOR MEMORY DEVICE (18326587)=== | | ===SEMICONDUCTOR MEMORY DEVICE (18326587)=== |
| Line 165: |
Line 65: |
| | '''Inventor''' | | '''Inventor''' |
| | Masanobu SHIRAKAWA | | Masanobu SHIRAKAWA |
| − |
| |
| − | '''Brief explanation'''
| |
| − | This abstract describes a semiconductor memory device that consists of two memory cells stacked on top of each other. The device also includes two word lines, which are used to control the memory cells, and a control unit that performs an erasing operation on the memory cells. During the erasing operation, the control unit applies a lower voltage to one word line and a higher voltage to the other word line.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.
| |
| | | | |
| | ===MEMORY DEVICE WHICH GENERATES OPERATION VOLTAGES IN PARALLEL WITH RECEPTION OF AN ADDRESS (18205915)=== | | ===MEMORY DEVICE WHICH GENERATES OPERATION VOLTAGES IN PARALLEL WITH RECEPTION OF AN ADDRESS (18205915)=== |
| Line 176: |
Line 70: |
| | '''Inventor''' | | '''Inventor''' |
| | Akio SUGAHARA | | Akio SUGAHARA |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a memory device that consists of several components. These components include a memory cell array, a voltage generation circuit, an input/output circuit, and a control circuit.
| |
| − |
| |
| − | The memory cell array stores data, while the voltage generation circuit generates one or more voltages that are supplied to the memory cell array. The input/output circuit receives an address, which indicates a specific region in the memory cell array that needs to be accessed.
| |
| − |
| |
| − | The control circuit is responsible for controlling the operations of the memory cell array. In this case, it specifically controls the supply of a non-selection voltage from the generated voltages. This non-selection voltage is supplied to the memory cell array before a ready/busy signal changes from a ready state to a busy state.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array, and a control circuit controlling operations of the memory cell array. The control circuit supplies a non-selection voltage of the voltages before a ready/busy signal changes from a ready state to a busy state.
| |
| | | | |
| | ===SEMICONDUCTOR MEMORY DEVICE (17882459)=== | | ===SEMICONDUCTOR MEMORY DEVICE (17882459)=== |
| Line 191: |
Line 75: |
| | '''Inventor''' | | '''Inventor''' |
| | Yousuke HAGIWARA | | Yousuke HAGIWARA |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a semiconductor memory device that has a comparator and a correction circuit. The comparator receives a read enable signal from an external source and outputs a signal in synchronization with it. The correction circuit is responsible for adjusting the duty cycle of this signal. It achieves this by using two variable current sources connected to different output portions of the comparator. The correction circuit adjusts the amount of current output from these sources to modify the duty cycles of the signals.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A semiconductor memory device includes a comparator that outputs a signal switched in synchronism with a read enable signal from outside and outputs the signal, and a correction circuit that adjusts the duty cycle of the signal. The correction circuit includes a variable current source connected to a first output portion of the comparator, and a variable current source connected to a second output portion of the comparator, and adjusts the amounts of current output from the current sources to adjust the duty cycles of signals.
| |
| | | | |
| | ===SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM (17899014)=== | | ===SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM (17899014)=== |
| Line 202: |
Line 80: |
| | '''Inventor''' | | '''Inventor''' |
| | Mitsuhiro ABE | | Mitsuhiro ABE |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a semiconductor memory device that has several components. It includes a first pad, which is a connection point for the device. The device also has a clock generation circuit that generates a specific type of clock called the first clock. This clock is then outputted through the first pad using an output circuit.
| |
| − |
| |
| − | The device also has a designation circuit that is responsible for selecting one of multiple time slots. These time slots are set based on the cycles of the first clock. Finally, there is a peak control circuit that performs an operation to generate a current peak at a specific timing that corresponds to the selected time slot.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A semiconductor memory device includes a first pad, a clock generation circuit configured to generate a first clock, an output circuit configured to output the first clock through the first pad, a designation circuit configured to designate one of a plurality of contiguous times slots, each of which is set with respect to clock cycles of the first clock, and a peak control circuit configured to execute an operation that generates a current peak, at a timing corresponding to the designated time slot.
| |
| | | | |
| | ===SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM (17902754)=== | | ===SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM (17902754)=== |
| Line 215: |
Line 85: |
| | '''Inventor''' | | '''Inventor''' |
| | Kenro KIKUCHI | | Kenro KIKUCHI |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a semiconductor storage device that consists of multiple strings, each containing several memory cell transistors. It also includes word lines, a bit line, a source line, and a control circuit. The control circuit is responsible for performing erase operations on the memory cell transistors. The control circuit can modify the settings of two types of erase-verify operations: one for an open block that has a memory cell transistor with an erase level, and another for a closed block that does not have a memory cell transistor with an erase block.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A semiconductor storage device of embodiments includes a block constituted with a plurality of strings each including a plurality of memory cell transistors, a plurality of word lines, a bit line, a source line, and a control circuit configured to perform erase operation on the plurality of memory cell transistors, and the control circuit changes setting of first erase-verify operation included in the erase operation for an open block including a memory cell transistor having an erase level and setting of second erase-verify operation included in erase operation for a closed block not including a memory cell transistor having an erase block.
| |
| | | | |
| | ===SEMICONDUCTOR MEMORY DEVICE (17899971)=== | | ===SEMICONDUCTOR MEMORY DEVICE (17899971)=== |
| Line 226: |
Line 90: |
| | '''Inventor''' | | '''Inventor''' |
| | Takeshi HIOKA | | Takeshi HIOKA |
| − |
| |
| − | '''Brief explanation'''
| |
| − | This abstract describes a semiconductor memory device that consists of a memory cell array, a word line, multiple bit lines, a sense amplifier, and a controller. The device performs a write operation using multiple program loops, each consisting of a program operation and a verify operation. During the program operation, the sense amplifier applies different voltages to the bit lines while a program voltage is applied to the word line.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A semiconductor memory device includes a memory cell array including a plurality of memory cells, a word line connected to the plurality of memory cells, a plurality of bit lines connected respectively to the plurality of memory cells, a sense amplifier connected to the plurality of bit lines, and a controller configured to execute a write operation in a plurality of program loops each including a program operation and a verify operation. The sense amplifier is configured to apply a first voltage, a second voltage higher than the first voltage, a third voltage higher than the second voltage, and a fourth voltage higher than the third voltage to first, second, third, and fourth bit lines of the plurality of bit lines, respectively, while a program voltage is applied to the word line in the program operation.
| |
| | | | |
| | ===MANUFACTURING METHOD OF ORIGINAL PLATE AND SEMICONDUCTOR DEVICE (18331066)=== | | ===MANUFACTURING METHOD OF ORIGINAL PLATE AND SEMICONDUCTOR DEVICE (18331066)=== |
| Line 237: |
Line 95: |
| | '''Inventor''' | | '''Inventor''' |
| | Hirotaka TSUDA | | Hirotaka TSUDA |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a type of plate used in imprint lithography, a process used in semiconductor device manufacturing. The plate has a patterned portion with a groove that is recessed from the surface to a certain depth. Inside the groove, there is a columnar portion that extends beyond the surface. This plate can be used to create replica templates through imprint lithography, which can then be used in semiconductor device manufacturing processes.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | According to one embodiment, an original plate for imprint lithography has a first surface side having a patterned portion thereon. The patterned portion includes a groove having a bottom surface recessed from a first surface to a first depth, and a columnar portion on the bottom surface and protruding from the bottom surface to extend beyond the first surface. The original plate may be used to form replica templates by imprint lithography processes. The replica templates can be used in semiconductor device manufacturing processes or the like.
| |
| | | | |
| | ===SEMICONDUCTOR DEVICE (17883690)=== | | ===SEMICONDUCTOR DEVICE (17883690)=== |
| Line 248: |
Line 100: |
| | '''Inventor''' | | '''Inventor''' |
| | Mayuka OJIMA | | Mayuka OJIMA |
| − |
| |
| − | '''Brief explanation'''
| |
| − | This abstract describes a semiconductor device that includes a substrate, a transistor, an insulating layer, and a first sealing portion. The substrate has two regions, with the second region surrounding the outer periphery of the first region. The transistor is located in the first region of the substrate. An insulating layer is placed above the transistor, covering both the first and second regions. The first sealing portion is used to separate the insulating layer and encircle the outer periphery of the first region within the second region. This first sealing portion contains a void.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A semiconductor device according to an embodiment includes a substrate, a transistor, an insulating layer, and a first sealing portion. The substrate includes a first region, and a second region provided to surround an outer periphery of the first region. The transistor is provided on the substrate in the first region. The insulating layer is provided above the transistor and over the first region and the second region. The first sealing portion is provided to divide the insulating layer and surround the outer periphery of the first region in the second region. The first sealing portion includes a first void.
| |
| | | | |
| | ===SEMICONDUCTOR STORAGE DEVICE (18330258)=== | | ===SEMICONDUCTOR STORAGE DEVICE (18330258)=== |
| Line 259: |
Line 105: |
| | '''Inventor''' | | '''Inventor''' |
| | Nobuaki OKADA | | Nobuaki OKADA |
| − |
| |
| − | '''Brief explanation'''
| |
| − | This abstract describes a semiconductor storage device that consists of two chips. The first chip has conductive layers arranged in a specific direction, a semiconductor pillar, and various contacts connected to power supply electrodes. The second chip has a semiconductor substrate, transistors, and contacts connected to the transistors. The two chips are bonded together so that their respective bonding electrodes are connected.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A semiconductor storage device includes first and second chips and first and second power supply electrodes. The first chip includes conductive layers arranged in a first direction, a semiconductor pillar extending in the first direction and facing the conductive layers, first contacts extending in the first direction and connected to the conductive layers, second contacts extending in the first direction and connected to a first power supply electrode, third contacts extending in the first direction, facing the second contacts in a direction crossing the first direction, and connected to the second power supply electrode, and first bonding electrodes connected to the first contacts. The second chip includes a semiconductor substrate, transistors provided on the semiconductor substrate, fourth contacts connected to the transistors, and second bonding electrodes connected to the fourth contacts. The first and second chips are bonded together so that respective first and second bonding electrodes are connected together.
| |
| | | | |
| | ===SYNDROME CALCULATION FOR ERROR DETECTION AND ERROR CORRECTION (18330669)=== | | ===SYNDROME CALCULATION FOR ERROR DETECTION AND ERROR CORRECTION (18330669)=== |
| Line 270: |
Line 110: |
| | '''Inventor''' | | '''Inventor''' |
| | Hironori UCHIKAWA | | Hironori UCHIKAWA |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a circuit that calculates syndromes in a composite field. This circuit includes a matrix product calculation circuit that generates syndrome bits by multiplying input data bits with a first arithmetic matrix. The first arithmetic matrix is obtained by multiplying a basis conversion matrix, which converts data from a Galois field to the composite field, with a second arithmetic matrix, which is a part of a parity check matrix.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A syndrome calculation circuit includes a matrix product calculation circuit. The matrix product calculation circuit is configured to generate syndrome bits in a composite field by calculating a matrix product of input data bits and a first arithmetic matrix. The first arithmetic matrix is a matrix product of a basis conversion matrix for converting a data string from a Galois field to the composite field and a second arithmetic matrix, which is at least a part of a parity check matrix.
| |
| | | | |
| | ===MEMORY SYSTEM (18314527)=== | | ===MEMORY SYSTEM (18314527)=== |
| Line 281: |
Line 115: |
| | '''Inventor''' | | '''Inventor''' |
| | Takehiko AMAKI | | Takehiko AMAKI |
| − |
| |
| − | '''Brief explanation'''
| |
| − | This abstract describes a memory system that consists of a semiconductor memory and a controller. The semiconductor memory is made up of blocks that contain memory cells. The controller is responsible for giving instructions to the semiconductor memory to perform two operations. In both operations, the semiconductor memory selects certain blocks and applies a voltage to all the memory cells within those selected blocks. However, the number of blocks to which the voltage is applied per unit time is greater in the second operation compared to the first operation.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.
| |
| | | | |
| | ===SEMICONDUCTOR MEMORY DEVICE (17929454)=== | | ===SEMICONDUCTOR MEMORY DEVICE (17929454)=== |
| Line 292: |
Line 120: |
| | '''Inventor''' | | '''Inventor''' |
| | Harumi SEKI | | Harumi SEKI |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a semiconductor memory device that consists of multiple layers stacked in a specific direction. These layers include a gate electrode layer, insulating layers, and a semiconductor layer. There is also a specific layer that contains silicon and nitrogen, with different regions containing or not containing fluorine. The concentration of fluorine in one region is higher than in the other region.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A semiconductor memory device according to an embodiment includes a stacked body in which a gate electrode layer and a first insulating layer are alternately stacked in a first direction, a semiconductor layer in the stacked body and extending in the first direction, a second insulating layer between the semiconductor layer and the stacked body, a third insulating layer provided between the second insulating layer and the stacked body, and a first layer between the second insulating layer and the third insulating layer. The first layer contains silicon and nitrogen and includes a first region between the gate electrode layer and the semiconductor layer and a second region between the first insulating layer and the semiconductor layer, the first region contains or does not contain fluorine, the second region contains fluorine, and a fluorine concentration of the second region is higher than a fluorine concentration of the first region.
| |
| | | | |
| | ===SEMICONDUCTOR MEMORY DEVICE (18330779)=== | | ===SEMICONDUCTOR MEMORY DEVICE (18330779)=== |
| Line 303: |
Line 125: |
| | '''Inventor''' | | '''Inventor''' |
| | Keisuke NAKATSUKA | | Keisuke NAKATSUKA |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a semiconductor storage device that consists of multiple layers of conductive material on a substrate. These layers are separated in one direction. There is also a pillar that goes through these layers and contains a semiconductor layer that extends in the same direction. The part of the pillar that intersects with the conductive layers acts as memory cells. Additionally, there is a second conductive layer above the first conductive layers, which is made of either a metal or a silicide, and it is in contact with the first semiconductor layer.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A semiconductor storage device of an embodiment includes a substrate, a plurality of first conductive layers, pillar, and a second conductive layer. The plurality of first conductive layers are provided above the substrate, and mutually separated in a first direction. The pillar is provided to penetrate the plurality of the first conductive layers, and includes a first semiconductor layer extending in the first direction. A part of the pillar that intersects with the first conductive layers are functioned as memory cells. The second conductive layer is provided above the plurality of first conductive layers and is in contact with the first semiconductor layer. The second conductive layer is made of a metal or a silicide.
| |
