Intel corporation (20240137029). SAMPLING FRACTIONAL-N PHASE-LOCKED LOOP WITH FEEDBACK SPUR COMPENSATION simplified abstract

SAMPLING FRACTIONAL-N PHASE-LOCKED LOOP WITH FEEDBACK SPUR COMPENSATION

Organization Name

intel corporation

Inventor(s)

Hao Luo of Milpitas CA (US)

Somnath Kundu of Hillsboro OR (US)

Brent R. Carlton of Portland OR (US)

SAMPLING FRACTIONAL-N PHASE-LOCKED LOOP WITH FEEDBACK SPUR COMPENSATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240137029 titled 'SAMPLING FRACTIONAL-N PHASE-LOCKED LOOP WITH FEEDBACK SPUR COMPENSATION

Simplified Explanation

The patent application describes a sampling phase-locked loop (PLL) with a compensation circuit designed to reduce ripples caused by a fractional N divider. The compensation circuit includes a ripple amplifier and a ripple divider to address this issue.

• The ripple amplifier amplifies the alternating current (AC) components of the output voltage (Vmain) from the main sampling circuit of the PLL.
• The amplified output voltage is then processed by a ripple integrator, which samples the minimum and maximum values to provide inputs to an operational amplifier (op amp).
• The op amp output is fed back to a digital-to-analog converter (DAC), which generates a compensation voltage (Vcomp) that is added to Vmain to produce a final output control voltage (Vctrl) for the voltage-controlled oscillator (VCO) of the PLL.

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1. 1. 1. Potential Applications

- Telecommunications - Wireless communication systems - Radar systems

1. 1. 1. Problems Solved

- Reducing ripples in a PLL due to the use of a fractional N divider - Improving the stability and performance of the PLL

1. 1. 1. Benefits

- Enhanced accuracy in frequency synthesis - Improved signal quality - Increased overall system performance

1. 1. 1. Potential Commercial Applications
         1. Optimizing Frequency Synthesis in Wireless Communication Systems

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1. 1. 1. Possible Prior Art

There may be prior art related to compensation circuits in PLLs to reduce ripples caused by fractional N dividers. Research in the field of PLL design and frequency synthesis may reveal similar approaches to addressing this issue.

1. 1. 1. Unanswered Questions
         1. How does the compensation circuit impact the overall power consumption of the PLL system?

The patent application does not provide information on the power consumption implications of the compensation circuit. Further research or testing may be needed to evaluate this aspect.

1. 1. 1. 1. Are there any limitations or trade-offs associated with the use of the compensation circuit in the PLL?

The patent application does not discuss any potential limitations or trade-offs that may arise from implementing the compensation circuit. Additional analysis or experimentation could shed light on this aspect.

Original Abstract Submitted

embodiments herein relate to a sampling phase-locked loop (pll) with a compensation circuit for reducing ripples due to the use of a fractional n divider. the compensation circuit includes a ripple amplifier and a ripple divider. the ripple amplifier receives an output voltage, vmain, of a main sampling circuit of the pll and amplifies its alternating current (ac) components. the amplified output voltage is provided to a ripple integrator which samples the minimum and maximum values to provide inputs to an operational amplifier (op amp). an output of the op amp is fed back to a digital-to-analog converter (dac), which provides a corresponding compensation voltage, vcomp. vcomp is added to vmain to provide a final output control voltage, vctrl, to control a voltage-controlled oscillator (vco) of the pll.