Intel corporation (20240137016). ADAPTIVE CLOCK GATING FOR IMPROVING WEAR OUT-INDUCED DUTY CYCLE SHIFT IN COMPUTER CLOCK NETWORK simplified abstract

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ADAPTIVE CLOCK GATING FOR IMPROVING WEAR OUT-INDUCED DUTY CYCLE SHIFT IN COMPUTER CLOCK NETWORK

Organization Name

intel corporation

Inventor(s)

Minki Cho of Portland OR (US)

Balkaran Gill of Cornelius OR (US)

Anisur Rahman of Beaverton OR (US)

Ketul B. Sutaria of Beaverton OR (US)

ADAPTIVE CLOCK GATING FOR IMPROVING WEAR OUT-INDUCED DUTY CYCLE SHIFT IN COMPUTER CLOCK NETWORK - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240137016 titled 'ADAPTIVE CLOCK GATING FOR IMPROVING WEAR OUT-INDUCED DUTY CYCLE SHIFT IN COMPUTER CLOCK NETWORK

Simplified Explanation

The patent application describes a system for clock gating in a computer core, where a device detects and sets the clock gating polarity based on certain conditions being satisfied.

  • Detection of enabled gating of a local clock in a computer core.
  • Determination of clock gating condition satisfaction based on the enabled gating.
  • Setting of clock gating polarity for the local clock based on the condition satisfaction.

Potential Applications

This technology could be applied in various computing devices to optimize power consumption and improve overall performance by efficiently managing clock signals.

Problems Solved

1. Power consumption optimization in computing devices. 2. Enhanced performance through efficient clock gating mechanisms.

Benefits

1. Improved energy efficiency. 2. Enhanced performance capabilities. 3. Extended battery life for portable devices.

Potential Commercial Applications

Optimizing power consumption in smartphones, laptops, tablets, and other electronic devices for longer battery life and improved performance.

Possible Prior Art

Prior art in clock gating mechanisms includes various techniques used in the industry to manage clock signals efficiently. One example is the use of clock gating cells to control clock signals in electronic devices.

Unanswered Questions

How does this technology compare to existing clock gating mechanisms in terms of efficiency and performance improvements?

The article does not provide a direct comparison with existing clock gating mechanisms, leaving the reader to wonder about the specific advantages of this new system.

Are there any potential drawbacks or limitations to implementing this clock gating system in different computing devices?

The article does not address any potential drawbacks or limitations that may arise from implementing this clock gating system in various computing devices, leaving room for further exploration and analysis.


Original Abstract Submitted

this disclosure describes systems, methods, and devices related to clock gating. a device may detect that gating of a local clock of a computer core is enabled; detect, based on the detection that the gating is enabled, that a clock gating condition for the local clock is satisfied; and set a clock gating polarity of the local clock based on the detection that the clock gating condition for the local clock is satisfied.