Intel corporation (20240134603). CONSTANT DIVISION AND MODULO VIA CARRYSAVE MODULO REDUCTION simplified abstract
Contents
CONSTANT DIVISION AND MODULO VIA CARRYSAVE MODULO REDUCTION
Organization Name
Inventor(s)
Theo Drane of El Dorado Hills CA (US)
Christopher Louis Poole of Folsom CA (US)
William Zorn of Folsom CA (US)
Emiliano Morini of El Dorado Hills CA (US)
CONSTANT DIVISION AND MODULO VIA CARRYSAVE MODULO REDUCTION - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240134603 titled 'CONSTANT DIVISION AND MODULO VIA CARRYSAVE MODULO REDUCTION
Simplified Explanation
The techniques described in the detailed description above enable the manufacturing of circuits with increased performance and efficiency when performing division by a constant number. One embodiment provides circuitry including an input circuit to receive an input value including a plurality of bits, a logarithmic tree coupled with the input circuit, the logarithmic tree configured to compute an array of values based on a plurality of multi-bit groups of the plurality of bits of the input value, each value in the array of values includes a modulus of a corresponding multi-bit group with respect to the constant, a binary array adder to compute a quotient of the division operation based on the array of values, the input value, and the constant, and an output circuit to output the quotient.
- Explanation:
- Circuitry designed to improve performance and efficiency in division operations by a constant number. - Input circuit receives input value with multiple bits. - Logarithmic tree computes values based on multi-bit groups of input value. - Binary array adder calculates quotient based on computed values, input value, and constant. - Output circuit provides the final quotient.
Potential Applications: - Computer processors - Digital signal processing - Cryptography systems
Problems Solved: - Enhancing performance and efficiency in division operations - Simplifying complex mathematical computations
Benefits: - Faster division operations - Reduced power consumption - Improved overall circuit efficiency
Potential Commercial Applications:
- Improving Division Efficiency in Circuitry ###
Possible Prior Art: - Previous circuit designs for division operations - Algorithms for optimizing mathematical computations
Unanswered Questions:
- How does this circuitry compare to traditional division methods in terms of speed and efficiency?
- Are there any limitations to the size of input values that can be processed by this circuitry?
Original Abstract Submitted
the techniques described in the detailed description above enable the manufacturing of circuits with increased performance and efficiency when performing division by a constant number. one embodiment provides circuitry including an input circuit to receive an input value including a plurality of bits, a logarithmic tree coupled with the input circuit, the logarithmic tree configured to compute an array of values based on a plurality of multi-bit groups of the plurality of bits of the input value, each value in the array of values includes a modulus of a corresponding multi-bit group with respect to the constant, a binary array adder to compute a quotient of the division operation based on the array of values, the input value, and the constant, and an output circuit to output the quotient.
