Intel corporation (20240126967). SEMI-AUTOMATIC TOOL TO CREATE FORMAL VERIFICATION MODELS simplified abstract
Contents
- 1 SEMI-AUTOMATIC TOOL TO CREATE FORMAL VERIFICATION MODELS
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SEMI-AUTOMATIC TOOL TO CREATE FORMAL VERIFICATION MODELS - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
SEMI-AUTOMATIC TOOL TO CREATE FORMAL VERIFICATION MODELS
Organization Name
Inventor(s)
Sparsa Roychowdhury of West Bengal (IN)
Geethabai Biradar of Karnataka (IN)
Theo Drane of El Dorado Hills CA (US)
Achutha Kiran Kumar M V of Bangalore (IN)
SEMI-AUTOMATIC TOOL TO CREATE FORMAL VERIFICATION MODELS - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240126967 titled 'SEMI-AUTOMATIC TOOL TO CREATE FORMAL VERIFICATION MODELS
Simplified Explanation
The techniques described in this patent application focus on automatically creating a software model for formal verification of semiconductor designs, enabling verification engineers to identify and fix bugs in both software and RTL designs efficiently.
- Simplified Explanation:
The patent application discusses techniques for automatically generating a software model for formal verification of semiconductor designs, allowing verification engineers to detect and correct bugs in software and RTL designs effectively.
- Explanation:
- Techniques for automatically creating a software model for formal verification of semiconductor designs - Enables verification engineers to identify and fix bugs in both software and RTL designs efficiently
Potential Applications
The technology described in this patent application can be applied in various industries such as semiconductor manufacturing, software development, and electronic design automation.
Problems Solved
1. Efficient bug detection and correction in software and RTL designs 2. Streamlining the formal verification process for semiconductor designs
Benefits
1. Saves significant design time 2. Reduces time to market for new products 3. Expands the scope of formal verification to cover both software and RTL bugs
Potential Commercial Applications
Optimizing formal verification processes in semiconductor manufacturing Improving software development workflows for complex designs Enhancing electronic design automation tools for efficient bug detection
Possible Prior Art
Prior art in the field of formal verification tools for semiconductor designs Existing techniques for software modeling in electronic design automation
Unanswered Questions
1. How do these techniques compare to existing methods for software modeling in formal verification? 2. What specific types of bugs can be effectively detected and fixed using this automated software model approach?
Original Abstract Submitted
described herein are techniques to automatically create a software model which covers the core functionality of a semiconductor design to be formally verified and can be easily consumed by a formal verification tool for software or semiconductor designs. these techniques enable verification engineers to expand the scope of formal verification to fix both software and rtl bugs, saving significant design time and reducing the time to market of for new products.
