Intel corporation (20240119255). METHODS AND APPARATUS TO TILE WALK A TENSOR FOR CONVOLUTION OPERATIONS simplified abstract

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METHODS AND APPARATUS TO TILE WALK A TENSOR FOR CONVOLUTION OPERATIONS

Organization Name

intel corporation

Inventor(s)

Yaniv Fais of Tel Aviv TA (IL)

Moshe Maor of Kiryat Mozking Z (IL)

METHODS AND APPARATUS TO TILE WALK A TENSOR FOR CONVOLUTION OPERATIONS - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240119255 titled 'METHODS AND APPARATUS TO TILE WALK A TENSOR FOR CONVOLUTION OPERATIONS

Simplified Explanation

The example apparatus described in the abstract is designed to perform a convolution on an input tensor using hardware accelerator circuitry. Here is a simplified explanation of the patent application abstract:

  • Parameters generator generates hardware execution parameters based on kernel and layer parameters.
  • Accelerator interface configures hardware accelerator circuitry based on the generated parameters.
  • Horizontal iterator controller determines completion of the first horizontal iteration.
  • Vertical iterator controller determines completion of the first vertical iteration.

Potential Applications

This technology can be applied in various fields such as image processing, signal processing, and machine learning for tasks like feature extraction, pattern recognition, and data analysis.

Problems Solved

1. Speed: The hardware accelerator speeds up the convolution process compared to traditional software implementations. 2. Efficiency: The apparatus optimizes hardware resources by generating execution parameters based on input parameters.

Benefits

1. Faster processing: The hardware accelerator improves the speed of convolution operations. 2. Resource optimization: The apparatus efficiently utilizes hardware resources for convolution tasks.

Potential Commercial Applications

Optimizing hardware acceleration for convolution tasks in industries such as computer vision, autonomous vehicles, medical imaging, and natural language processing.

Possible Prior Art

Prior art may include patents or research papers related to hardware acceleration for convolution operations in neural networks or image processing applications.

Unanswered Questions

How does this apparatus handle different kernel sizes and layer parameters?

The apparatus generates hardware execution parameters based on the kernel and layer parameters, but it is not specified how it handles variations in kernel sizes or different layer configurations.

What is the cost-effectiveness of implementing this hardware accelerator in comparison to traditional software-based convolution methods?

The abstract does not provide information on the cost implications of using this hardware accelerator compared to traditional software implementations.


Original Abstract Submitted

an example apparatus to perform a convolution on an input tensor includes a parameters generator to: generate a horizontal hardware execution parameter for a horizontal dimension of the input tensor based on a kernel parameter and a layer parameter; and generate a vertical hardware execution parameter for a vertical dimension of the input tensor based on the kernel parameter and the layer parameter; an accelerator interface to configure a hardware accelerator circuitry based on the horizontal and vertical hardware execution parameters; a horizontal iterator controller to determine when the hardware accelerator circuitry completes the first horizontal iteration of the convolution; and a vertical iterator controller to determine when the hardware accelerator circuitry completes the first vertical iteration of the convolution.