Intel corporation (20240114627). ENHANCED SUBTRACTIVE ETCH ANISOTROPY USING ETCH RATE GRADIENT simplified abstract

ENHANCED SUBTRACTIVE ETCH ANISOTROPY USING ETCH RATE GRADIENT

Organization Name

intel corporation

Inventor(s)

Jeremy Ecton of Gilbert AZ (US)

Robert Alan May of Chandler AZ (US)

Suddhasattwa Nad of Chandler AZ (US)

Srinivas V. Pietambaram of Chandler AZ (US)

Brandon C. Marin of Gilbert AZ (US)

ENHANCED SUBTRACTIVE ETCH ANISOTROPY USING ETCH RATE GRADIENT - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240114627 titled 'ENHANCED SUBTRACTIVE ETCH ANISOTROPY USING ETCH RATE GRADIENT

Simplified Explanation

The patent application describes a package substrate with a core made of insulative material, first conductive traces on the core's surface, and buildup layers with second conductive traces in an organic dielectric material. The first conductive traces consist of a first metal and a second metal, with a higher concentration of the first metal near the core and a non-uniform variation in concentration between regions.

• The package substrate includes a core made of insulative material.
• First conductive traces are in contact with the core's surface.
• Buildup layers contain second conductive traces in an organic dielectric material.
• The first conductive traces consist of a first metal and a second metal.
• The concentration of the first metal is higher near the core and varies non-uniformly between regions.

Potential Applications

This technology could be applied in the manufacturing of electronic devices, such as integrated circuits, where a reliable and efficient package substrate is required.

Problems Solved

This innovation solves the problem of ensuring proper electrical connectivity and signal transmission within electronic devices by providing a package substrate with optimized conductive traces.

Benefits

The benefits of this technology include improved performance and reliability of electronic devices, as well as potentially reducing manufacturing costs through efficient substrate design.

Potential Commercial Applications

• "Optimized Package Substrate Design for Electronic Devices" - This title is SEO optimized for potential commercial applications of the technology.

Possible Prior Art

There may be prior art related to package substrates with conductive traces, but specific examples are not provided in the patent application.

How does this technology compare to existing package substrate designs in terms of performance and cost-effectiveness?

The article does not provide a direct comparison with existing technologies, so it is unclear how this innovation stands out in terms of performance and cost.

Are there any limitations or challenges in implementing this technology on a large scale in manufacturing processes?

The patent application does not address any potential limitations or challenges that may arise when implementing this technology on a large scale in manufacturing processes.

Original Abstract Submitted

embodiments provides for a package substrate, including: a core comprising insulative material; first conductive traces in contact with a surface of the core; and buildup layers in contact with the first conductive traces and the surface of the core, the buildup layers comprising second conductive traces in an organic dielectric material. the first conductive traces comprise at least a first metal and a second metal, the first conductive traces comprise a first region proximate to and in contact with the core and a second region distant from the core, parallel and opposite to the first region, a relative concentration of the first metal to the second metal is higher in the first region than in the second region, and the relative concentration of the first metal to the second metal between the first region and the second region varies non-uniformly.