Intel corporation (20240113088). INTEGRATED CIRCUIT PACKAGES WITH HYBRID BONDED DIES AND METHODS OF MANUFACTURING THE SAME simplified abstract

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INTEGRATED CIRCUIT PACKAGES WITH HYBRID BONDED DIES AND METHODS OF MANUFACTURING THE SAME

Organization Name

intel corporation

Inventor(s)

Omkar Karhade of Chandler AZ (US)

Nitin Deshpande of Chandler AZ (US)

Harini Kilambi of Portland OR (US)

Jagat Shakya of Hillsboro OR (US)

Debendra Mallik of Chandler AZ (US)

INTEGRATED CIRCUIT PACKAGES WITH HYBRID BONDED DIES AND METHODS OF MANUFACTURING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240113088 titled 'INTEGRATED CIRCUIT PACKAGES WITH HYBRID BONDED DIES AND METHODS OF MANUFACTURING THE SAME

Simplified Explanation

The abstract describes an integrated circuit (IC) package with two dies bonded together using metal vias for electrical coupling.

  • The IC package includes a first die with a bulk semiconductor region, a second die with a bulk semiconductor region, a first bonding layer with first metal vias, and a second bonding layer with second metal vias.
  • The first and second dies are electrically coupled through the metal vias in the bonding layers.

Potential Applications

This technology could be applied in:

  • Semiconductor manufacturing
  • Electronics packaging

Problems Solved

This technology helps in:

  • Improving electrical coupling between dies
  • Enhancing the performance of integrated circuits

Benefits

The benefits of this technology include:

  • Increased efficiency in electronic devices
  • Enhanced reliability of integrated circuits

Potential Commercial Applications

The potential commercial applications of this technology could be in:

  • Consumer electronics
  • Telecommunications industry

Possible Prior Art

One possible prior art for this technology could be:

  • Metal vias used in semiconductor packaging

Unanswered Questions

How does this technology impact the overall size of the integrated circuit package?

This article does not provide information on how the integration of metal vias affects the size of the IC package. Further research or analysis may be needed to understand this aspect.

What are the specific materials used for the bonding layers in this technology?

The abstract does not mention the specific materials used for the bonding layers with metal vias. Understanding the materials could provide insights into the performance and reliability of the IC package.


Original Abstract Submitted

methods, apparatus, systems, and articles of manufacture are disclosed includes an integrated circuit (ic) package including a first die including a first surface and a second surface opposite the first surface, the first surface defined by a bulk semiconductor region of the first die, a second die including a third surface and a fourth surface opposite the third surface, the third surface defined by a bulk semiconductor region of the second die, the fourth surface facing towards the second surface, a first bonding layer between the second and fourth surfaces, the first bonding layer including first metal vias disposed therein, and a second bonding layer between the second and fourth surfaces, the second bonding layer including second metal vias disposed therein, the first bonding layer in direct contact with the second bonding layer, ones of the first metal vias in direct contact with ones of the second metal vias to electrically couple the first die to the second die.

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