Intel corporation (20240105677). RECONSTITUTED WAFER WITH SIDE-STACKED INTEGRATED CIRCUIT DIE simplified abstract
Contents
- 1 RECONSTITUTED WAFER WITH SIDE-STACKED INTEGRATED CIRCUIT DIE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 RECONSTITUTED WAFER WITH SIDE-STACKED INTEGRATED CIRCUIT DIE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
RECONSTITUTED WAFER WITH SIDE-STACKED INTEGRATED CIRCUIT DIE
Organization Name
Inventor(s)
Abhishek Anil Sharma of Portland OR (US)
Tahir Ghani of Portland OR (US)
Sagar Suthram of Portland OR (US)
Anand Murthy of Portland OR (US)
Wilfred Gomes of Portland OR (US)
Pushkar Ranade of San Jose CA (US)
RECONSTITUTED WAFER WITH SIDE-STACKED INTEGRATED CIRCUIT DIE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240105677 titled 'RECONSTITUTED WAFER WITH SIDE-STACKED INTEGRATED CIRCUIT DIE
Simplified Explanation
The integrated circuit device described in the abstract consists of two IC dies coupled to a substrate with fill material between them. This configuration allows for efficient integration of multiple components in a single device.
- Two IC dies are connected to a substrate.
- Fill material is used between the IC dies to enhance integration.
Potential Applications
This technology could be applied in:
- Consumer electronics
- Telecommunications
- Automotive industry
Problems Solved
This technology helps solve:
- Space constraints in electronic devices
- Improving efficiency in circuit design
Benefits
The benefits of this technology include:
- Compact design
- Enhanced performance
- Cost-effective manufacturing
Potential Commercial Applications
The potential commercial applications of this technology include:
- Mobile devices
- Networking equipment
- Automotive electronics
Possible Prior Art
One possible prior art for this technology could be the use of stacked IC dies in semiconductor devices to increase functionality and performance.
Unanswered Questions
How does this technology impact power consumption in electronic devices?
The abstract does not provide information on how this technology affects power consumption in electronic devices. Further research is needed to understand the energy efficiency implications of this innovation.
What are the potential challenges in manufacturing integrated circuit devices with multiple dies?
The abstract does not address the potential challenges in manufacturing integrated circuit devices with multiple dies. Exploring the manufacturing process and potential obstacles could provide valuable insights into the practical implementation of this technology.
Original Abstract Submitted
an integrated circuit device includes a first ic die with a first front surface, a first back surface, and a first side surface along opposed edges of the first front surface and the first back surfaces of the first ic die, a second ic die with a second front surface, a second back surface, and a second side surface along opposed edges of the second front surface and second back surface of the second ic die, a substrate coupled to the first side surface of the first ic die and the second side surface of the second ic die, and fill material between one of the first front surface and the first back surface of the first ic die and one of the second front surface and second back surface of the second ic die. other embodiments are disclosed and claimed.
