Intel corporation (20240103079). INFIELD PERIODIC DEVICE TESTING WHILE MAINTAINING HOST CONNECTIVITY simplified abstract

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INFIELD PERIODIC DEVICE TESTING WHILE MAINTAINING HOST CONNECTIVITY

Organization Name

intel corporation

Inventor(s)

Rakesh Kandula of Doddakannelli Bangalore (IN)

Sankaran Menon of Austin TX (US)

Rolf Kuehnis of Portland OR (US)

INFIELD PERIODIC DEVICE TESTING WHILE MAINTAINING HOST CONNECTIVITY - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240103079 titled 'INFIELD PERIODIC DEVICE TESTING WHILE MAINTAINING HOST CONNECTIVITY

Simplified Explanation

The abstract describes a patent application related to testing a device while a system is operational, using scan test circuitry and preservation circuitry to maintain data in host connectivity registers during testing.

  • Scan test circuitry allows for testing of the device while the system is operational.
  • Preservation circuitry preserves the data stored in host connectivity registers during testing.
  • In-operation testing ensures the device can return to full operation without reprogramming the registers.
  • Performance and user experience are not degraded during testing.

Potential Applications

This technology could be applied in various industries where testing of devices while in operation is necessary, such as telecommunications, data centers, and industrial automation.

Problems Solved

This technology solves the problem of having to shut down a system for testing, as well as the need to reprogram host connectivity registers after testing, saving time and resources.

Benefits

The benefits of this technology include improved efficiency in testing processes, reduced downtime for systems, and overall cost savings for companies.

Potential Commercial Applications

Potential commercial applications of this technology include device testing in live environments, system maintenance without disruption, and ensuring continuous operation of critical systems.

Possible Prior Art

One possible prior art could be the use of scan test circuitry in testing devices, but the specific application of preserving data in host connectivity registers during in-operation testing may be a novel aspect of this technology.

Unanswered Questions

How does the preservation circuitry ensure the data in host connectivity registers is maintained during testing?

The preservation circuitry likely includes mechanisms to store and protect the data in the registers, such as backup power sources or redundant memory storage.

What are the potential risks or limitations of using scan test circuitry and preservation circuitry in device testing?

Potential risks could include compatibility issues with existing systems, increased complexity in device design, and potential security vulnerabilities if not implemented properly.


Original Abstract Submitted

embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to performing testing of a device while a system is operational. a device may include computing circuitry and host connectivity registers. host connectivity registers contain configuration and memory mapping data programmed by system software upon power up of the device and computing system. the data contained in host connectivity registers should be always maintained while the computing system is operational. scan test circuitry may be implemented, providing the ability to test the device while the system is operational. preservation circuitry preserves or maintains the data stored in host connectivity registers allowing in-operation testing of the device, ensuring the device the ability to return to full operation at the end of in-operation testing without requiring system software to reprogram the host connectivity registers. by using scan-sealing methods and/or preserving the data in host connectivity registers during in-operation testing, performance and user experience are not degraded.