Intel Corporation patent applications published on September 28th, 2023

AGITATION MONITORING SYSTEM FOR PLATING PROCESS (17702839)

Abstract

The present disclosure is directed to a monitoring system for a plating process using a monitoring device including a metrology component for collecting agitation intensity data on at least one agitation component within a plating equipment and transferring the collected agitation intensity data to a process control station.

Inventor

Adrian BAYRAKTAROGLU

WAFER LEVEL ELECTRON BEAM PROBER (17701323)

Abstract

Wafer level electron beam prober systems, devices, and techniques, are described herein related to providing wafer level testing for fabricated device structures. Such wafer level testing contacts a first side of a die of a wafer with a probe to provide test signals to the die under test and performs e-beam imaging of the first side of the die while the test signals are provided to the die under test.

Inventor

Xianghong Tong

OPPORTUNISTIC BATTERY CHARGING WITH A PROGRAMMABLE POWER ADAPTER (17705012)

Abstract

Techniques and mechanisms for opportunistically charging a battery with a programmable power adapter. In an embodiment, a charger circuit is to be coupled between the programmable power adapter and a load circuit which is coupled to the battery. Bypass circuitry is coupled to selectively enable a bypassing of the charger circuit. Based on a state of charge of the battery, a controller circuit identifies a power delivery scheme which includes both an operational mode of the programmable power adapter, and an activation state of the switch circuit. The controller configures the identified power delivery scheme by signaling that the programmable power adapter is to be transitioned to the operational mode. In another embodiment, the operational mode is based on communications which are compatible with a Universal Serial Bus (USB) standard protocol.

Inventor

Udaya Natarajan

SAVING AND RESTORING CONFIGURATION AND STATUS INFORMATION WITH REDUCED LATENCY (17682032)

Abstract

In one embodiment, an apparatus includes: a port circuit to receive a configuration write from a source circuit; a save restore memory coupled to the port circuit to store information of a plurality of control and status registers (CSRs); and a configuration network coupled to the port circuit, the configuration network coupled to a plurality of nodes, each of the plurality of nodes comprising at least one CSR. The port circuit may be configured to send the configuration write to a first node of the plurality of nodes and to the save restore memory. Other embodiments are described and claimed.

Inventor

Deepak Rameshkumar Tanna

FACILITATING IMPROVED USE OF STOCHASTIC ASSOCIATIVE MEMORY (18040145)

Abstract

Methods, apparatus, systems, and articles of manufacture are disclosed to facilitate improved use of stochastic associative memory. Example instructions cause at least one processor to: generate a hash code for data to be stored in a stochastic associative memory (SAM); compare the hash code with centroids of clusters of data stored in the SAM; select a first one of the clusters corresponding to a first one of the centroids that is closest to the hash code; determine whether a selected number of hash codes stored in the SAM exceeds a threshold; in response to the selected number exceeding the threshold: query a controller for sizes of the clusters; and determine, based on the query, that a second one of the clusters includes an unbalanced size; and select a third one of the clusters to associate with a second number of hash codes corresponding to the second one of the clusters.

Inventor

Dipanjan Sengupta

RESERVATION OF MEMORY IN MULTIPLE TIERS OF MEMORY (18084258)

Abstract

Examples described herein relate to a memory controller, when connected to at least one memory device in a multi-tiered memory system comprising a near memory and far memory, is to allocate a region of the near memory to a requester based on receipt of a request. In some examples, the memory controller includes circuitry to transmit at least one memory read command and address information to the multi-tiered memory system to read data from the multi-tiered memory system and circuitry to transmit at least one memory write command and address information to the multi-tiered memory system to write data to the multi-tiered memory system, wherein the near memory comprises at least one memory connected to the memory controller via a memory interface and the far memory comprises at least one memory connected to the memory controller via a network.

Inventor

Slawomir PUTYRSKI

PRECISE LONGITUDINAL MONITORING OF MEMORY OPERATIONS (18327474)

Abstract

A processor includes a memory subunit that includes a status register and an execution engine unit to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit is to store a piece of information, related to a status of the load operation, in the status register. The processor also includes logic to, responsive to detection of retirement of the load operation, store memory information in memory-related fields of a record of a memory buffer. The memory information includes auxiliary information (AUX) and access latency information, wherein one of the auxiliary information or the access latency information includes the piece of information, from the status register, stored in a particular field of the memory-related fields.

Inventor

Ahmad YASIN

METHODS AND APPARATUS TO PERFORM AN ENHANCED S3 PROTOCOL TO UPDATE FIRMWARE WITH A BOOT SCRIPT UPDATE (18040146)

Abstract

Methods, apparatus, systems, and articles of manufacture perform an enhanced S3 protocol to update firmware with a Boot Script update are disclosed. An example apparatus includes a management agent to store a firmware update into memory; and request an operating system (OS) to enter into an S3 sleep state; the OS to, in response to the request from the management agent, enter into the S3 sleep state and trigger an interrupt; and a basic input/output system (BIOS) to, in response to the interrupt from the OS update a Boot Script according to the firmware update; and wake up the OS with a wake vector.

Inventor

Di Zhang

METHODS AND APPARATUS TO PERFORM A PSEUDO-S3 PROTOCOL TO UPDATE FIRMWARE AND/OR ACTIVATE NEW FIRMWARE WITH A WARM RESET (18040147)

Abstract

Methods, apparatus, systems, and articles of manufacture to perform a pseudo-S3 protocol to update firmware and/or activate new firmware with a warm reset are disclosed. An example apparatus includes an advanced configuration and power interface (ACPI) to: initiate a pseudo-sleep event in response to identifying a firmware update; and assert a power button event, the power button event to cause an operating system (OS) to prepare to enter into a sleep state; a basic input/output system (BIOS) to: initiate a warm reset in response to the OS preparing to enter the sleep state, the warm reset to update firmware according to the firmware update; and transmit a wake vector to the OS to continue operation.

Inventor

Mohan Kumar

PROCESSOR HARDWARE AND INSTRUCTIONS FOR VECTORIZED FUSED AND-XOR (17703194)

Abstract

A method comprises fetching, by fetch circuitry, an encoded vectorized AND-XOR instruction comprising an opcode, a first source identifier, a second source identifier, a third source identifier, and a destination identifier, decoding, by decode circuitry, the decoded vectorized AND-XOR instruction to generate a decoded vectorized AND-XOR instruction, and executing, by execution circuitry, the decoded vectorized AND-XOR instruction to retrieve operands representing a product coefficient at an index position from the first source, a coefficient of a first polynomial from the second source, and a coefficient of a second polynomial from the third source, perform, in an atomic fashion, a vectorized AND-XOR operation to generate updated value of the product coefficient, and store the product coefficient of the output polynomial in a register file accessible to the execution circuitry.

Inventor

Andrew H. Reinders

SYSTEMS, APPARATUS, ARTICLES OF MANUFACTURE, AND METHODS FOR DATA DRIVEN NETWORKING (18189813)

Abstract

Systems, apparatus, articles of manufacture, and methods are disclosed. An example edge compute device disclosed herein includes interface circuitry, machine readable instructions, and programmable circuitry to execute the machine readable instructions to configure compute resources of the edge compute device based on a first resource demand associated with a first location of the edge compute device, detect a change in location of the edge compute device to a second location, and in response to detection of the change in location, reconfigure the compute resources of the edge compute device based on a second resource demand associated with the second location.

Inventor

Roya Doostnejad

REGISTER REPLAY STATE MACHINE (18326918)

Abstract

Register operations to cause a processor unit to enter into a management operating mode are stored in a dedicated buffer in the processor unit and are executed by the processor unit when the processor unit is to enter into a management operating mode. The register operations can be stored in the buffer during computing system startup or by out-of-band provisioning during computing system runtime. The register operations can save a state of the processor unit as part of entering the management operating mode and restore the state when the processor unit exits the management operation mode. In computing systems comprising multiple processor units, the register operations can cause one of the processor units to execute management operating mode instructions and one or more other processor units to enter into an idle mode while the processor units are in the management operating mode.

Inventor

Xueyan Wang

DEVICE, SYSTEM AND METHOD FOR PROVIDING A HIGH AFFINITY SNOOP FILTER (17705015)

Abstract

Techniques and mechanisms for efficiently providing access to cached data. In an embodiment, a cache coherency engine comprises circuitry to provide a snoop filter which stores entries each corresponding to a respective line of one or more caches. The one or more caches comprise a first cache which includes a first set, and the snoop filter includes a first plurality of sets which are each configured to be available to represent a line of the first set. In another embodiment, the one or more caches comprise multiple caches which each comprise a respective first set, wherein, for each set of the first plurality of sets, any line in the multiple caches which is to be represented by that each set is to be a line in the respective first sets of the multiple caches.

Inventor

Leon Polishuk

CHIPLET ARCHITECTURE FOR LATE BIND SKU FUNGIBILITY (17702271)

Abstract

Described herein is a modular parallel processor comprising an active base die including hardware logic, interconnect logic, and a plurality of chiplet slots and a plurality of chiplets vertically stacked on the active base die and coupled with the plurality of chiplet slots of the active base die. The plurality of chiplets is interchangeable during assembly of the modular parallel processor and include a group of hardware logic chiplets having a plurality of different functional units and a group of memory chiplets having a plurality of different memory devices. The hardware logic chiplets and the memory chiplets interconnect via the interconnect logic within the active base die.

Inventor

Mark C. Davis

INTERFACE BRIDGE BETWEEN INTEGRATED CIRCUIT DIE (18327043)

Abstract

An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

Inventor

Jeffrey Erik Schulz

CHIPLET ARCHITECTURE CHUNKING FOR UNIFORMITY ACROSS MULTIPLE CHIPLET CONFIGURATIONS (17702235)

Abstract

Described herein is a modular parallel processor and associated manufacturing method in which the parallel processor is assembled from multiple chiplets that populate multiple chiplet slots of an active base chiplet die. The multiple chiplets are tested to determine characteristics of the chiplet, such as a number of functional units or a power consumption metric for the chiplet. The multiple chiplet slots can be configured to be populated by one or more chunks of multiple chiplets, where each chunk has a pre-determined collective value. The pre-determined collective value can be a total number of functional execution cores within a chunk or a collective power metric for the chunk.

Inventor

Mark C. Davis

MODULAR PERIPHERY TILE FOR INTEGRATED CIRCUIT DEVICE (18327045)

Abstract

Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.

Inventor

Chee Hak Teh

COMPRESSION USING A FLAT MAPPING IN VIRTUAL ADDRESS SPACE (17702301)

Abstract

Described herein is a graphics processor comprising a processing resource configured to perform processing operations, a codec configured to compress and decompress data associated with the processing operations, and circuitry configured to calculate a metadata address for a compressed surface based on a flat virtual memory address mapping between the address of the compressed surface and the metadata address. The compressed surface is to store data associated with a processing operation to be performed by the processing resource and the metadata address is a virtual address that stores compression metadata for the compressed surface. The circuitry can configure the codec to access the compressed surface based on the compression metadata.

Inventor

Vidhya Krishnan

DISPLAY VIRTUALIZATION (17827305)

Abstract

Described herein is a partitional graphics processor including a display controller including hardware display virtualization. One embodiment provides a graphics processor comprising a system interface including a first virtual interface and a second virtual interface, a render engine to perform graphics rendering operations, and a display engine including hardware display virtualization. The render engine is configured to perform a first rendering operation in response to a command received via the first virtual interface and a second rendering operation in response to a command received via the second virtual interface. The display engine configured to present output of the first rendering operation via a first physical display plane that is associated with the first virtual interface and present output of the second rendering operation via a second physical display plane that is associated with the second virtual interface.

Inventor

David Cowperthwaite

REGISTRATION METROLOGY TOOL USING DARKFIELD AND PHASE CONTRAST IMAGING (17705436)

Abstract

The present disclosure is directed to an inspection system for registration metrology and defect detection using darkfield and phase contrast imaging optical systems. The present system includes a transmitted light mode and diffracted light mode to enable imaging of low contrast features on blank EUV masks and semiconductor wafers. In an aspect, this system combines the optics for darkfield and phase contrast imaging, and may also include the optics for brightfield imaging, to provide analyzed data on registration errors and surface defects.

Inventor

Deepan KISHORE KUMAR

DEEP LEARNING FOR DENSE SEMANTIC SEGMENTATION IN VIDEO WITH AUTOMATED INTERACTIVITY AND IMPROVED TEMPORAL COHERENCE (18131650)

Abstract

Techniques related to automatically segmenting video frames into per pixel dense object of interest and background regions are discussed. Such techniques include applying a segmentation convolutional neural network (CNN) to a CNN input including a current video frame, a previous video frame, an object of interest indicator frame, a motion frame, and multiple feature frames each including features compressed from feature layers of an object classification convolutional neural network as applied to the current video frame to generate candidate segmentations and selecting one of the candidate segmentations as a final segmentation of the current video frame.

Inventor

Anthony Rhodes

ENHANCING HIERARCHICAL DEPTH BUFFER CULLING EFFICIENCY VIA MASK ACCUMULATION (18189873)

Abstract

Embodiments described herein provide for a technique to improve the culling efficiency of coarse depth testing. One embodiment provides for a graphics processor that is configured to perform a method to track a history of source fragments that are tested against a destination tile. When a combination of partial fragments sum to full coverage, the most conservative source far depth value is used instead of the previous destination far depth value. When the combination sums to partial coverage, the previous destination far depth value is retained.

Inventor

Saikat Mandal

TECHNOLOGIES FOR CURRENT BIASING FOR MEMORY CELLS (17703921)

Abstract

Techniques for current biasing for memory cells are disclosed. In the illustrative embodiment, a source follower sets a voltage on a bitline of a memory cell. The current through the source follower is limited by a current mirror in series with the source follower. When additional current is required that the source follower cannot supply, a feedback transistor is activated to provide additional current. Additionally, in some embodiments, the current through the feedback transistor is copied to a current mirror, and the copied current is used to sense the state of the memory cell.

Inventor

Jonathan Y. Wang

IMPLANTATION THROUGH AN ETCH STOP LAYER (17656366)

Abstract

An integrated circuit includes a first layer comprising dielectric material. One or both of an interconnect feature and a device are within the dielectric material of the first layer. The integrated circuit further includes a second layer above the first layer, where the second layer includes dielectric material. A third layer is between the first layer and the second layer. In an example, the third layer can be, for example, an etch stop layer or a liner layer or barrier layer. In an example, an impurity is within the first layer and the third layer. In an example, the impurity has a detectable implant depth profile such that a first distribution of the impurity is within the first layer and a second distribution of the impurity is within the third layer.

Inventor

Moshe Dolejsi

ALIGNED PITCH-QUARTERED PATTERNING FOR LITHOGRAPHY EDGE PLACEMENT ERROR ADVANCED RECTIFICATION (18205456)

Abstract

Aligned pitch-quartered patterning approaches for lithography edge placement error advanced rectification are described. For example, a method of fabricating a semiconductor structure includes forming a first patterned hardmask on a semiconductor substrate. A second hardmask layer is formed on the semiconductor substrate. A segregated di-block co-polymer is formed on the first patterned hardmask and on the second hardmask layer. Second polymer blocks are removed from the segregated di-block co-polymer. A second patterned hardmask is formed from the second hardmask layer and a plurality of semiconductor fins is formed in the semiconductor substrate using first polymer blocks as a mask. A first fin of the plurality of semiconductor fins is removed. Subsequent to removing the first fin, a second fin of the plurality of semiconductor fins is removed.

Inventor

Charles H. WALLACE

PACKAGE LAYERS FOR STRESS MONITORING AND METHOD (17705878)

Abstract

A semiconductor package comprises a package substrate comprised of comprised of layers of a first material. The semiconductor package includes an integrated circuit (IC) attached to the substrate at a first surface of the IC through a plurality of vias. The semiconductor package includes at least one interface layer comprised of an interface material different from the first material and sealed from exposure to air. The interface material can comprise a moisture-sensitive nonconductive material and can be disposed within the package substrate or between the first surface of the IC and the package substrate, among other locations. Other systems, apparatuses and methods are described.

Inventor

Jan Proschwitz

SUBSTRATE FOR IMPROVED HEAT DISSIPATION AND METHOD (17703400)

Abstract

A semiconductor package comprises a package substrate comprised of at least a first layer of dielectric material including a portion of diamond dust material. The diamond dust material is comprised of diamond dust particles. The semiconductor package includes at least one electrical connection coupled through layers of the package substrate.

Inventor

Carlton Hanna

PACKAGING ARCHITECTURE WITH EDGE RING ANCHORING (17583485)

Abstract

A microelectronic assembly is provided, comprising: an interposer having a first face and a second face opposite to the first face; a package substrate coupled to the first face; an integrated circuit die coupled to the second face; and an edge ring in the interposer. The interposer comprises a core comprising a first dielectric material and a redistribution layer (RDL), the RDL being on the first face or the second face, the RDL comprising a second dielectric material different from the first dielectric material, and the edge ring comprises: a metal trace in contact with the second dielectric material, the metal trace being along a periphery of the interposer, and a plurality of metal vias through the RDL, the plurality of metal vias in contact with the metal trace.

Inventor

Xavier Francois Brun

AIRGAPS USED IN BACKEND MEMORY STRUCTURES (17704410)

Abstract

Techniques are provided herein for forming backend memory structures with airgaps in an interconnect region above semiconductor devices. The airgaps may be provided between conductive features, such as wordlines, to reduce parasitic capacitance. An interconnect region above a plurality of semiconductor devices includes any number of interconnect layers. A first interconnect layer includes first conductive layers (e.g., wordlines) extending in a first direction with airgaps between adjacent first conductive layers. A second interconnect layer over the first interconnect layer includes at least portions of memory cells over corresponding first conductive layers. A third interconnect layer over the second interconnect layer includes a second conductive layer (e.g., bitline) extending in a second direction over one or more of the at least portions of memory cells. The presence of airgaps between the first conductive layers allows for a tighter pitch between memory cells and reduced total energy consumption among the memory cells.

Inventor

Miriam R. Reshotko

SIZE AND EFFICIENCY OF DIES (18202136)

Abstract

An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.

Inventor

Mathew J. MANUSHAROW

BGA STIFFENER ATTACHMENT WITH LOW EOLIFE ADHESIVE STRENGTH AT HIGH SOLDER JOINT STRESS AREA GENERATED FROM ENABLING LOAD (17703768)

Abstract

Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate, and a die coupled to the package substrate. In an embodiment, the electronic package further comprises a stiffener on the package substrate surrounding the die. In an embodiment, the stiffener is a ring with one or more corner regions and one or more beams. In an embodiment, each beam is between a pair of corner regions, and the one or more corner regions have a first thickness and the one or more beams have a second thickness that is greater than the first thickness.

Inventor

Phil GENG

GAN 3D POWER BLOCK (17706454)

Abstract

Embodiments disclosed herein include a coupled inductor. In an embodiment, the coupled inductor comprises a first inductor and a second inductor. In an embodiment, the first inductor can be coupled to the first inductor. In an embodiment, the coupled inductor further comprises a first switch coupled to the first inductor, where the first switch comprises gallium and nitrogen, and a second switch coupled to the second inductor, where the second switch comprises gallium and nitrogen.

Inventor

Ahmed ABOU-ALFOTOUH

BACKSIDE PROCESSING OF FINS IN FIN BASED TRANSISTOR DEVICES (17656490)

Abstract

An integrated circuit includes a first source region, a first drain region, a first fin having (i) a first upper region laterally between the first source region and the first drain region and (ii) a first lower region below the first upper region, and a first gate structure on at least top and side surfaces of the first upper region. The integrated circuit further includes a second source region, a second drain region, a second fin having (i) a second upper region laterally between the second source region and the second drain region and (ii) a second lower region below the second upper region, and a second gate structure on at least top and side surfaces of the second upper region. In an example, a first vertical height of the first lower region is different from a second vertical height of the second lower region by at least 2 nanometers (nm).

Inventor

Tao Chu

REPLACEMENT METAL GATES TO ENHANCE TRANSISTOR STRAIN (18204231)

Abstract

Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.

Inventor

Mark T. BOHR

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING BACKSIDE CONTACT WITH ENHANCED AREA RELATIVE TO EPITAXIAL SOURCE (17706218)

Abstract

Gate-all-around integrated circuit structures having backside contact with enhanced area relative to an epitaxial source or drain region are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. A conductive structure is vertically beneath and in contact with one of the first epitaxial source or drain structures. The conductive structure is along an entirety of a bottom of the one of the first epitaxial source or drain structures, and the conductive structure can also be along a portion of sides of one of the first epitaxial source or drain structures.

Inventor

Joseph D'SILVA

TRANSISTOR GATE STACKS WITH THICK HYSTERETIC ELEMENTS (17702593)

Abstract

Disclosed herein are transistor gate-channel arrangements with transistor gate stacks that include thick hysteretic elements (i.e., hysteretic elements having a thickness of at least 10-15 nanometers, e.g., between 55 and 100 nanometers), and related methods and devices. Transistor gate stacks disclosed herein include a multilayer gate insulator having a thick hysteretic element and an interface layer, where the thick hysteretic element is between the interface layer and a gate electrode material, and the interface layer is between the thick hysteretic element and a channel material of a transistor. The interface layer may be a dielectric material with an effective dielectric constant of at least 20 and/or be a dielectric material that is thinner than about 3 nanometers. Such an interface layer may help improve gate control and allow use of thick hysteretic elements while maintaining transistor performance in terms of, e.g., gate leakage, carrier mobility, and subthreshold swing.

Inventor

Abhishek A. Sharma

LOW RADIATION HIGH SYMMETRY INDUCTOR (17704050)

Abstract

A circuitry including a first S-shaped winding and a second S-shaped winding configured to form a figure-8 inductive structure; a first terminal coupled to a first end of the first S-shaped winding and a second terminal coupled to a first end of the second S-shaped winding, wherein the first terminal is configured to receive a first positive signal and the second terminal is configured to receive a first negative signal; a third terminal coupled to a second end of the first S-shaped winding and a fourth terminal coupled to a second end of the second S-shaped winding, wherein the third terminal is configured to receive a second negative signal and the fourth terminal is configured to receive a second positive signal; wherein a magnetic flux is concentrated at an intersection of the first S-shaped winding and the second S-shaped winding when a first current flows through them.

Inventor

Run LEVINGER

HIGH PRECISION SCALABLE PACKAGING ARCHITECTURE BASED ON RADIO FREQUENCY SCANNING (17700819)

Abstract

Embodiments of a microelectronic assembly comprise a plurality of transceiver modules, each transceiver module including a first antenna; a printed circuit board (PCB); and a reflector module coupled to the PCB and separated from the plurality of transceiver modules by a space. The reflector module comprises: a substrate having a first side and an opposing second side, the first side being proximate to the plurality of transceiver modules, an antenna-array on the first side of the substrate, the antenna-array including a plurality of second antennas; a first integrated circuit (IC) die on the second side of the substrate; and a second IC die on the second side of the substrate. The first IC die comprises radio frequency (RF) switches configured to operate at electromagnetic frequencies between 20 kHz and 1 THz, and the second IC die comprises memory cell arrays and digital logic circuits.

Inventor

Georgios Dogiamis

LOW PROFILE IMPEDANCE-TUNABLE AND CROSS-TALK CONTROLLED HIGH SPEED HYBRID SOCKET INTERCONNECT (17703730)

Abstract

Embodiments disclosed herein include sockets and socket architectures. In an embodiment, a socket comprises a substrate. In an embodiment, an opening is provided through the substrate. In an embodiment, an elastomeric pin inserted into the opening. In an embodiment, the elastomeric pin is electrically conductive.

Inventor

Emad S. AL-MOMANI

NON-CONTACT POWER RECEIVER APPARATUS (18191329)

Abstract

A non-contact power transmission apparatus accurately determines the kind of object that is placed on the charging deck of the non-contact power transmission apparatus, and, only when a non-contact power receiving apparatus is placed on the power transmission apparatus, allows power transmission and data communication to take place, thereby accurately determining the state of the receiver side and efficiently controlling the transmission of power. In the power transmission apparatus, the power supplied to the non-contact power receiving apparatus is measured, and the output power of the wireless power signal output from two different cores is controlled, thereby allowing the charging operation to be stably conducted even if the non-contact power receiving apparatus is moved anywhere on the power transmission apparatus. The power transmission apparatus improves both the reliability of operation of the non-contact charging system, and the competitiveness of related products, such as portable terminals, battery packs and the like.

Inventor

Chun-Kil Jung

VOLTAGE REGULATOR DRIVERS AND CONVERTER STAGES (17704950)

Abstract

Power driver circuits may be used to provide higher voltage capabilities beyond what may managed by a single transistor. To reduce or eliminate effects associated with a stacked transistor voltage driver, a secondary stacked transistor voltage driver may be separated from a primary stacked transistor voltage driver, where the secondary driver is driven using time-shifted control signals. A switching schema may be used to interleave the several cells of a single continuous capacitive voltage regulator. A multi-stage approach may include both a number of fixed-ratio or multi-ratio capacitive voltage converter stages and final stage that is switched out of phase from the preceding stages, where the final stage includes a continuously scalable capacitive converter.

Inventor

Nicolas Butzen

DISTRIBUTED RADIOHEAD SYSTEM (DRS) AND CLOCKING, CALIBRATION, AND SYNCHRONIZATION FOR DRS (18041804)

Abstract

In various aspects of this disclosure, a communication device is provided. The communication device may include a first radiohead circuit including a first transceiver chain configured to transmit a first radio frequency signal associated with a first transmission configuration and to transmit a second radio frequency signal associated with a second transmission configuration a second radiohead circuit comprising a second transceiver chain configured to receive the first radio frequency signal and the second radio frequency signal, and one or more processors configured to determine a first signal parameter associated with the first radio frequency signal received at the second transceiver chain and a second signal parameter associated with the second radio frequency signal received at the second transceiver chain, and to determine a preferred transmission configuration for the first transceiver chain by using the first signal parameter and the second signal parameter.

Inventor

Rotem BANIN

LINK PERFORMANCE PREDICTION USING SPATIAL LINK PERFORMANCE MAPPING (18023699)

Abstract

In one embodiment, a current path of a mobile device is determined based on radio signals between the mobile device and a base station, which indicates a sequence of positions of the mobile device over a current time window. A future path of the mobile device is then predicted based on the current path, which indicates a sequence of predicted future positions of the mobile device over a future time window. A link performance prediction (LPP) is then generated for the mobile device based on the future path of the mobile device and a base station coverage map. The base station coverage map indicates a radio signal quality across a base station coverage area, which is represented as a three-dimensional (3D) coordinate space. Moreover, the LPP indicates a predicted performance of a radio link between the mobile device and the base station during the future time window.

Inventor

Jonas Svennebring

APPARATUS, SYSTEM AND METHOD OF COMMUNICATING A PHYSICAL LAYER PROTOCOL DATA UNIT (PPDU) INCLUDING A TRAINING FIELD (17972200)

Abstract

Some demonstrative embodiments include apparatuses, devices, systems and methods of communicating a PPDU including a training field. For example, an Enhanced Directional Multi-Gigabit (DMG) (EDMG) wireless communication station may be configured to determine one or more Orthogonal Frequency Division Multiplexing (OFDM) Training (TRN) sequences in a frequency domain based on a count of one or more 2.16 Gigahertz (GHz) channels in a channel bandwidth for transmission of an EDMG PPDU including a TRN field; generate one or more OFDM TRN waveforms in a time domain based on the one or more OFDM TRN sequences, respectively, and based on an OFDM TRN mapping matrix, which is based on a count of the one or more transmit chains; and transmit an OFDM mode transmission of the EDMG PPDU over the channel bandwidth, the OFDM mode transmission comprising transmission of the TRN field based on the one or more OFDM TRN waveforms.

Inventor

Artyom Lomayev

SCS ID MAPPINGS TO MLD LINKS (17953074)

Abstract

Methods, apparatuses, and computer readable media for stream classification service (SCS) identification to multi-link device (MLD) link in wireless local area network (WLAN) are disclosed. Apparatuses of a non-access point (AP) or station (STA) of a MLD are disclosed, where the apparatuses comprise processing circuitry configured to: encode for transmission, to a second MLD, a stream classification service (SCS) request frame, the SCS comprising a quality of service (QoS) element, the QoS element comprising a link identification (LinkID) subfield indicating a LinkID, where the SCS request frame comprises a SCS identification (ID)(SCSID) subfield, the SCSID subfield indicating a SCSID to be mapped to the LinkID and further configured to decode, from the second MLD, a SCS response frame to the SCS request frame, the SCS request frame indicating whether the LinkID is mapped to the SCSID.

Inventor

Laurent Cariou

APPARATUS, SYSTEM, AND METHOD OF PEER-TO-PEER (P2P) COMMUNICATION (18091023)

Abstract

For example, a first wireless communication device may be configured to determine a negotiated bootstrapping mechanism based on a first message-exchange including Peer-to-Peer (P2P) messages exchanged with a second wireless communication device; to pair the first wireless communication device with the second wireless communication device according to the negotiated bootstrapping mechanism; to derive a Pairwise Master Key Security Association (PMKSA) based on a second message-exchange with the second wireless communication device, e.g., after pairing with the second wireless communication device; and to determine an encryption key according to a third message exchange with the second wireless communication device based on the PMKSA. For example, the encryption key may be configured to encrypt a P2P communication with the second wireless communication device.

Inventor

Emily H. Qi

COMPUTING WORKLOAD MANAGEMENT IN NEXT GENERATION CELLULAR NETWORKS (18007898)

Abstract

Various embodiments generally may relate to the field of wireless communications. For example, some embodiments may relate to enabling augmented computing as a service or network capability for sixth-generation (6G) networks. For example, some embodiments may be directed to the operation of a compute control client (Comp CC) at the UE side, and a compute control function (Comp CF) and compute service function (Comp SF) at the network side, which are referred to herein as “compute plane” functions to handle computing related control and user traffic.

Inventor

Zongrui DING

DETECTION OF LTE ENB AND UE EMITTERS USING SIGNAL PROCESSING ALGORITHMS FOR FEATURE RECOGNITION (17705611)

Abstract

An apparatus and system for determining and identifying communication signals are described. Characteristics of the waveform for received signals are determined. Statistical and/or Cyclostationary Signal Processing algorithms are used on the characteristics to identify each signals as a communication signal having a particular protocol. Autocorrelation, spectral correlation, and power Cepstrum, among others, are used to identify the signal using periodic characteristics of the waveform in the frequency domain. Rogue devices that do not adhere to the protocol are identified and actions taken accordingly.

Inventor

Maya Mani

WIRELESS COMMUNICATION SYSTEMS (18173100)

Abstract

A wireless station may include one or more processors. The one or more processors may determine data is to be transferred. The one or more processors may also determine a data type of the data corresponds to a priority data type. In addition, the one or more processors may provide a data type signal indicating the data type corresponds to the priority data type. Further, the one or more processors may receive a data type confirmation signal in response to the data type signal. The one or more processors may create a dedicated bearer with a network device based on the data type confirmation signal. The one or more processors may also instruct the data to be transferred via the dedicated bearer.

Inventor

Anshu AGARWAL

METHODS AND DEVICES TO ESTABLISH AND MAINTAIN CONNECTIONS WITH MULTIPLE COMMUNICATION DEVICES (18161894)

Abstract

A communication device may include a processor configured to establish a connection with one or more peripheral devices in response to a disconnection from an external communication device, determine that the external communication device is connectable based on radio communication signals received from the external communication device, and encode a message to be transmitted to the one or more peripheral devices in response to the determination that the external communication device is connectable, wherein the message is configured to cause the one or more peripheral devices to perform a high duty cycle advertising in accordance with a Bluetooth communication protocol.

Inventor

Harish MITTY

METAL ORGANIC FRAMEWORKS (MOFS) FILLER FOR ENABLING LOW CTE AND LOW DIELECTRIC CONSTANT PCB (17703704)

Abstract

Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a printed circuit board (PCB), where the PCB comprises a glass weave, a resin, and metal organic frameworks (MOFs) disposed within the resin. In an embodiment, a package substrate is coupled to the PCB, and a die is coupled to the package substrate.

Inventor

Yang JIAO

MIRROR-CORE MOUNTING MULTIPLE COMPUTER PROCESSOR MODULES FOR MINIMIZED TRACE LENGTH (17703717)

Abstract

Embodiments disclosed herein include a computer system. In an embodiment, the computer system comprises a printed circuit board assembly (PCBA) with a first surface and a second surface opposite from the first surface. In an embodiment, a first computer processor module is coupled to the first surface of the PCBA, and a second computer processor module is coupled to the second surface of the PCBA. In an embodiment, the first computer processor module is communicatively coupled to the second computer processor module through an electrical path that passes through a thickness of the PCBA.

Inventor

Carl WILLIAMS

FLOW ENHANCEMENT STRUCTURE FOR IMMERSION COOLED ELECTRONIC SYSTEMS (18203904)

Abstract

An apparatus is described that includes a flow enhancement structure to enhance a flow of immersion bath liquid specifically through space between fins of a heat sink and/or across a base of a heat sink.

Inventor

Liguang DU