INTERNATIONAL BUSINESS MACHINES CORPORATION patent applications published on October 5th, 2023

Patent applications for INTERNATIONAL BUSINESS MACHINES CORPORATION on October 5th, 2023

Autonomous Vehicle System With On-The-Road Recharge Capability (17657141)

Inventor Saraswathi Sailaja Perumalla

Brief explanation

The abstract describes a system where one autonomous vehicle can charge another autonomous vehicle while they are both driving on a road. This charging is done through a wired connection. Multiple vehicles can be charged simultaneously while driving together with the charging vehicle.

Abstract

A system for electrically charging a first autonomous vehicle (that is, the charged vehicle) by a second autonomous vehicle (that is, charging vehicle) through a wired connection while the vehicles are travelling over a roadway (for example, an interstate highway). In some embodiments, multiple charged vehicles may be charged at the same time while driving in tandem with the charging vehicle.

Positional Delivery and Encoding by Oligonucleotides of Biological Cells for Single Cell Sequencing (POS SEQ) (18207585)

Inventor Pablo Meyer Rojas

Brief explanation

This abstract describes techniques for delivering and encoding biological cells in a way that allows for single cell RNA sequencing. The method involves introducing molecular probes into the cells, which encode the position of the cells within a biological sample. This allows for accurate identification and analysis of individual cells during sequencing. The abstract also mentions the provision of a system for implementing this positional delivery and encoding process.

Abstract

Techniques for positional delivery and position encoding by oligonucleotides of biological cells for single cell RNA sequencing are provided. In one aspect, a method of positional delivery and encoding of cells in a biological sample includes: encoding the cells in the biological sample for single cell sequencing by delivering molecular probes inside the cells that encode a position of the cells in the biological sample. A system for positional delivery and encoding of cells in a biological sample is also provided.

Optical Sensor System for Quantitative Colorimetric Liquid Analysis (18203022)

Inventor Minhua Lu

Brief explanation

The abstract describes techniques for accurately analyzing the color and turbidity of liquid samples. It introduces an optical detector that includes a vessel for holding the sample, a light source, and two sensors positioned on different sides of the vessel. The sensors are used to measure the color and turbidity of the liquid. The abstract also mentions methods for quantitatively measuring an analyte and analyzing color and turbidity. Overall, the techniques aim to provide accurate and reliable results for liquid analysis.

Abstract

Techniques for quantitative colorimetric liquid analysis with color and turbidity correction are provided. In one aspect, an optical detector includes: a vessel for containing a liquid sample; a light source on a first side of the vessel; a first sensor on a second side of the vessel opposite the first side and along a light path of the light source; and a second sensor on a third side of the vessel at an angle θ with respect to the light path. A method for quantitative measurement of an analyte is also provided, as is a method for color and turbidity analysis.

ELECTRICAL-OPTICAL BRIDGE CHIP AND INTEGRATED CIRCUIT PACKAGING STRUCTURE (17712332)

Inventor Frank Robert Libsch

Brief explanation

The abstract describes a bridge chip used in an integrated circuit (IC) packaging structure. This bridge chip includes converters that convert electrical signals to optical signals and vice versa. The chip is connected to host chips through wiring patterns, and it has an optical interface that outputs optical signals from the backside of the chip. The chip also has electrical through links that output electrical signals generated by the host chips. The packaging structure includes a substrate with a trench, where the bridge chip is placed. The host chips are directly connected to the top surface of the bridge chip and the substrate. Optical signals are output from the packaging structure through an opening in the bottom surface of the substrate.

Abstract

A bridge chip of an IC packaging structure includes E/O and O/E converters and a first wiring pattern interconnecting the converters to host chips and a second wiring pattern electrically connected to the host chips. An optical interface outputs the optical signals from a backside surface of the bridge chip. The optical interface receives optical signals through the backside surface. Electrical through links connected to the second wiring pattern output electrical signals generated by the host chips through the backside surface of the bridge chip. The packaging structure includes substrate with a trench provided in the top surface of the substrate and the bridge chip disposed in the trench. The host chips are directly connected to the top surface of the bridge chip and the top surface of the substrate. Optical signals are output from the packaging structure through an opening in the bottom surface of the substrate.

METHOD FOR FORMING CONTINUOUS LINE-END TO LINE-END SPACES WITH SPACER ASSISTED LITHOGRAPHY-ETCH-LITHOGRAPHY ETCH PROCESSES (17657493)

Inventor Allen GABOR

Brief explanation

The abstract describes a method and device for improving and streamlining a lithography-etch-lithography-etch (LELE) process called spacer assisted lithography-etch-lithography-etch (SALELE). This process involves using a spin-on-material layer to fill gaps between spacers, which helps protect the spaces between lines created by a cut shape. The method also includes a final resist layer with varying critical dimensions (CDs). By using the spin-on-material layer, it becomes possible to design metal structures in the back end of line (BEOL) with continuous line-end to line-end spacing above a minimum that can be patterned using only a cut mask and spacer process.

Abstract

Method and apparatus for improved and efficient spacer assisted lithography-etch-lithography etch (SALELE) processes that utilize a spin-on-material layer, where the spin-on-material layer fills gaps between spacers to protect line-end to line-end spaces created by a cut shape. The method and structures also include a final resist layer with varying critical dimensions (CDs). The use of the spin-on-material enables back end of line (BEOL) metal designs with continuous line-end to line-end spacing above a minimum that can be patterned with a cut mask and spacer only process.

ROUNDING HEXADECIMAL FLOATING POINT NUMBERS USING BINARY INCREMENTORS (17705036)

Inventor MICHAEL KLEIN

Brief explanation

The abstract describes a method for rounding hexadecimal floating point numbers using binary incrementors. It involves incrementing two subsets of bits in the operand, generating an intermediate result based on the carryout of the second incrementor, and generating a final rounded result based on the carryout of the first incrementor and certain bits of the intermediate result. The purpose of this method is to simplify the rounding process for hexadecimal floating point numbers.

Abstract

Rounding hexadecimal floating point numbers using binary incrementors, including: incrementing, by a first incrementor, a first subset of bits of an operand comprising a binary hexadecimal floating point operand; incrementing, by a second incrementor, a second subset of bits of the operand; generate an intermediate result based on a carryout of the second incrementor; and generate an incremented result based on a carryout of the first incrementor and one or more of: a first bit of the intermediate result or the carryout of the second incrementor.

VERIFYING THE CORRECTNESS OF A LEADING ZERO COUNTER (17704938)

Inventor MICHAEL KLEIN

Brief explanation

The abstract describes a method for checking the accuracy of a leading zero counter. This involves several steps: 

1. Creating a binary representation (bit vector) based on a given input value, where each entry in the vector indicates whether the corresponding digit in the input value is zero or not. 2. Calculating the number of leading zeros in the input value by analyzing the bit vector. 3. Generating a bit mask with a number of leading ones equal to the count of leading zeros. 4. Creating a second bit vector with a one at the same index as the first occurrence of zero in the bit mask. 5. Verifying the accuracy of the leading zero count by comparing the first bit vector with either the bit mask or the second bit vector (or both).

Abstract

Verifying the correctness of a leading zero counter, including: generating, based on an input value comprising a plurality of digits, a first bit vector, wherein each entry of the first bit vector indicates whether a corresponding digit of the input value is equal to zero; calculating, based on the first bit vector, a leading zero count for the input value; generating a bit mask comprising a number of leading ones equal to the leading zero count; generating a second bit vector comprising a one at a same index as a first occurring zero in the bit mask; and verifying the leading zero count based on the first bit vector and one or more of the bit mask and the second bit vector.

INTEGRATION FLOW WORKLOAD DISTRIBUTION (17706736)

Inventor Chengxuan Xing

Brief explanation

The abstract explains that an integration flow can be enhanced by using a pattern from a pattern library. This pattern consists of a group of nodes that perform a specific function within the integration flow. The pattern also includes an endpoint, which is capable of executing the group of nodes. By incorporating this pattern into the integration flow, the endpoint can be utilized to execute the specific group of nodes, improving the overall functionality of the integration flow.

Abstract

An integration flow can be improved with the use of a pattern identified from a pattern library. The identified pattern can include a snippet of nodes which are functionally equivalent to a subset of nodes in the integration flow. The pattern also lists an endpoint capable of performing the snippet of nodes. The integration flow can therefore be updated to cause the endpoint to perform the snippet of nodes.

AUTOMATIC CONTAINER SPECIFICATION FILE CREATION AND UPDATE FOR A CODEBASE (17657605)

Inventor Gabriele PICCO

Brief explanation

This abstract describes a method for improving a codebase in a computer system. The method involves automatically updating one or more container specification files with any changes made to the codebase.

Abstract

Embodiments for providing an enhanced codebase in a computing environment by a processor. One or more container specification files may be automatically updated with one or more changes to a codebase.

SIMULATION OF USER ACTIONS IN COMPUTER ENVIRONMENT (17700908)

Inventor Sho Ayuba

Brief explanation

This abstract describes a process where a user application is launched and a clone of that application is created. The clone then detects a trigger within the application, which is a simulation of a user action. In response to detecting the trigger, the clone executes the user action and displays the results to the user of the application.

Abstract

A launch of a user application is detected and a clone instance of that user application is initiated. A trigger is detected. The trigger is within the user application and is for a simulation of a user action. The user action is executed in the clone instance in response to detecting the trigger. The results of the user action are displayed to a user of the user application.

IMAGE MANAGEMENT FOR CONTAINER RUNTIMES (17706721)

Inventor Xun Pan

Brief explanation

This abstract describes a method for managing images in container runtimes. It explains that the approach involves downloading an image from a repository and extracting both the content data of the application and the management data related to the application and the container runtime from the image. If the content data is not already stored in the image sharing file system, both the content data and the management data are stored in the file system. However, if the content data is already stored in the file system, only the management data is stored.

Abstract

Disclosed is an approach for image management for container runtimes. A first image of a first application for a first container runtime can be downloaded from an image repository providing the first image. Content data of the first application and management data corresponding to the first application and the first container runtime can be extracted from the first image. Both the content data of the first application and the management data corresponding to the first application and the first container runtime can be stored in an image sharing file system in response to the content data of the first application being not stored in the image sharing file system. Only the management data corresponding to the first application and the first container runtime can be stored in the image sharing file system in response to the content data of the first application being stored in the image sharing file system.

QUANTUM COMPUTER PERFORMANCE ENHANCEMENT (17657706)

Inventor Mattias Fitzpatrick

Brief explanation

The abstract describes techniques for improving the calibration and performance of quantum computers. It introduces three main components: a monitoring job component, a modeler component, and a calibration agent. The monitoring job component executes monitoring jobs on the quantum computer, while the modeler component determines the system state parameter values of the quantum computer at a given time based on the output data generated by the quantum computer during the execution of the monitoring jobs. The calibration agent then determines a calibration strategy for calibrating the parameters of the quantum computer based on the system state parameter values. Additionally, the calibration agent calculates a reward that considers the benefits and costs associated with performing calibrations, and uses this reward to update a calibration policy that guides the calibration strategy for quantum computers.

Abstract

Techniques for enhanced calibration and performance of quantum computers are presented. A monitoring job component can execute monitoring jobs on a quantum computer. A modeler component can determine respective quantum computer system state parameter values at a given time based on parameter values at respective time instances, the parameter values determined from output data generated by the quantum computer in response to execution of the monitoring jobs. A calibration agent can determine a calibration strategy relating to ordering of performance of calibration tasks to calibrate at least one parameter associated with the quantum computer based on the quantum computer system state parameter values. Calibration agent can determine a reward relating to benefits and costs associated with performing calibrations of quantum computers, and, based on the reward, can update a calibration policy that can be used to determine or update the calibration strategy for calibrating parameters associated with quantum computers.

CENTRAL RANDOMIZED SCHEDULER FOR HYPOTHESIS-BASED WORKLOADS (17708609)

Inventor Sven Sterbling

Brief explanation

The abstract describes a system that consists of a memory and a processor. The processor is capable of performing various operations. These operations involve loading rules and workloads related to the system's environment, retrieving data about the available workloads, the execution environment, and the historical workload data. The operations also include selecting a workload to be executed in the execution environment and determining the appropriate settings for its execution. Finally, the workload is submitted to an execution queue to be executed according to the specified settings.

Abstract

A system may include a memory and a processor in communication with the memory. The processor may be configured to perform operations. The operations may include loading environment rules and available workloads and retrieving workload data for the available workloads, execution environment data of an execution environment, and historic workload data. The operations may include selecting a workload for the execution environment and determining execution settings for the workload. The operations may include submitting the workload to an execution queue for execution in the execution environment according to the execution settings.

TICKET QUEUE FOR CONTROLLING COMPUTE PROCESS ACCESS TO SHARED DATA AND COMPUTE RESOURCES (17656991)

Inventor George Diedrich GRISTEDE

Brief explanation

The abstract describes a method for controlling access to shared data and resources in a computing system. When a compute process needs to access shared resources or data to perform a task, it creates a ticket file in a ticket queue directory. The compute process can proceed with the task only if its ticket file is at the front of the queue, based on a ticket ordering algorithm applied by the compute process. After completing the task, the compute process removes its ticket from the queue.

Abstract

Controlling compute process access to shared data and compute resources includes, responsive to a compute process determining that access to at least one of shared resources and shared data is necessary to perform a compute task, creating, by the compute process, a ticket file belonging to the compute process in a ticket queue directory. The compute process is allowed to proceed performing the compute task upon determining that the ticket file is first in line in a ticket queue of the ticket queue directory, according to a ticket ordering algorithm independently applied by the compute process. Subsequent to completing the compute task, the compute process removes the ticket from the ticket queue directory.

DYNAMIC FACTORING AND COMPOSING WORKFLOWS (17657017)

Inventor Michael JOHNSTON

Brief explanation

This abstract describes a technology that allows for the dynamic creation and combination of workflows in a computer system. The system can identify functional blocks within stored workflows and determine similarities and relationships between these blocks. Based on these similarities and relationships, the system can suggest the use of certain blocks in new workflows.

Abstract

Various embodiments are provided for dynamically factoring and composing workflows in a computing environment by one or more processors in a computing system. Subgraphs (e.g., blocks) of workflows stored in a workflow library may be identified. The subgraphs may be functional blocks such as, for example, the functional blocks may perform a logical task. Similarities and relationships may be identified between one or more of the blocks of one or more workflows. One or more blocks may be suggested for use in workflow opportunities of target workflows based on the identified associated similarities and relationships.

FUNCTION DEFINED EVENT STREAMS FROM MULTIPLE EVENT STREAMS AND EVENTS (17657369)

Inventor Bharat Bhushan

Brief explanation

The abstract describes techniques for creating output streams based on combinations of events published in an event-driven architecture. These techniques involve receiving an output function that specifies criteria for selecting events from one or more event notification streams. The event notification streams are then parsed, and events are selected to create a new event notification stream. This new stream contains events that correspond to instances of the output function when given a set of input events. When an event meeting the criteria specified in the output function is published in the original event notification streams, the new event notification stream publishes an event that represents the output value of the output function.

Abstract

Disclosed are techniques for function-defined output streams corresponding to combinations of events published to one or more event notification streams in an event-driven architecture with a plurality of event notification streams. An output function is received defining a combination of event notifications with criteria for selecting which event notifications to combine from one or more event notification streams. The one or more event notification streams are parsed, and event notifications are selected to initialize a new event notification stream, where event notifications in this stream correspond to instances of the output function when provided a set of event notifications from the one or more event notification streams as input values. When an event notification is published to the one or more event notification streams meeting the criteria specified in the output function, the new event notification stream publishes an event notification corresponding to an output value from the output function.

AUTOMATIC NODE CRASH DETECTION AND REMEDIATION IN DISTRIBUTED COMPUTING SYSTEMS (17708235)

Inventor Kevin Allen Hughes

Brief explanation

This abstract describes a computer-based method for detecting and addressing a crashed node in a distributed computing environment. The method involves detecting indications of a node crash, confirming the crash by performing tests on the node, and then initiating a remediation process to address the crashed node.

Abstract

A computer-implemented method includes: detecting, by one or more processors, an indication that suggests a node has crashed, wherein the node is included in a distributed computing environment; in response to the detecting, confirming by the one or more processors whether the node has crashed by performing a set of probes on the node; and in response to the confirming that the node has crashed, initiating by the one or more processors a remediation of the node.

CACHE LINE COMPRESSION PREDICTION AND ADAPTIVE COMPRESSION (17696089)

Inventor Bulent Abali

Brief explanation

The abstract describes a central processing unit (CPU) system that has a CPU core with an adaptive cache compressor. This compressor is designed to monitor the cache's miss profile, which refers to the frequency at which data is not found in the cache. The adaptive cache compressor compares this miss profile to a predetermined miss threshold. Depending on this comparison, the compressor decides whether to enable compression of the cache.

Abstract

A central processing unit (CPU) system including a CPU core can include an adaptive cache compressor, which is capable of monitoring a miss profile of a cache. The adaptive cache compressor can compare the miss profile to a miss threshold. Based on this comparison, the adaptive cache compressor can determine whether to enable compression of the cache.

PREEMPTIVE TRACKING OF REMOTE REQUESTS FOR DECENTRALIZED HOT CACHE LINE FAIRNESS TRACKING (17713267)

Inventor Tu-An T. Nguyen

Brief explanation

This abstract describes a method for preemptively tracking remote requests for decentralized hot cache line fairness tracking. It involves requesting authority for a cache line and querying for any outstanding requests for that cache line. The method then receives one or more responses regarding the outstanding requests. Before receiving the authority for the cache line, the method preemptively tracks the outstanding requests in a requested structure associated with the cache line.

Abstract

Embodiments are for preemptive tracking of remote requests for decentralized hot cache line fairness tracking. Authority is requested for a cache line in conjunction with querying for outstanding requests for the cache line. One or more responses are received regarding the outstanding requests for the cache line. In response to receiving the one or more responses regarding the outstanding requests and in advance of receiving the authority for the cache line, the outstanding requests are preemptively tracked in a requested structure associated with the cache line.

USING A SHADOW COPY OF A CACHE IN A CACHE HIERARCHY (17709807)

Inventor Yair Fried

Brief explanation

The abstract describes a method of using a shadow copy of a level 1 (L1) cache in a cache hierarchy. This shadow copy is maintained in the cache hierarchy and is updated with memory content changes to the L1 cache a few pipeline cycles after the L1 cache is updated.

Abstract

Aspects include using a shadow copy of a level 1 (L1) cache in a cache hierarchy. A method includes maintaining the shadow copy of the L1 cache in the cache hierarchy. The maintaining includes updating the shadow copy of the L1 cache with memory content changes to the L1 cache a number of pipeline cycles after the L1 cache is updated with the memory content changes.

SHADOW POINTER DIRECTORY IN AN INCLUSIVE HIERARCHICAL CACHE (17712510)

Inventor Ashraf ElSharif

Brief explanation

This abstract describes a computer system that consists of a processor core and a memory system. The memory system includes two levels of cache: a first cache and a second cache. The first cache is higher in the memory hierarchy and stores a set of entries called first-cache entries. The second cache is lower in the hierarchy and stores a set of entries called second-cache entries. 

The first cache keeps track of these entries using a directory, which contains information about each first-cache entry. The second cache, on the other hand, maintains a shadow pointer directory (SPD) that maps each first-cache entry to a corresponding second-cache entry at a lower-level cache location.

In simpler terms, this computer system has two levels of cache memory. The first cache is faster and stores a certain set of entries, while the second cache is slower and stores a different set of entries. The first cache keeps track of its entries using a directory, and the second cache uses a shadow pointer directory to map the entries from the first cache to its own entries.

Abstract

A computer system includes a processor core and a memory system in signal communication with the processor core. The memory system includes a first cache and a second cache. The first cache is arranged at a first level of a hierarchy in the memory system and is configured to store a plurality of first-cache entries. The second cache is arranged at a second level of the hierarchy that is lower than the first level, and stores a plurality of second-cache entries. The first cache maintains a directory that contains information for each of the first-cache entries. The second cache maintains a shadow pointer directory (SPD) that includes one or more SPD entries that maps each of the first-cache entries to a corresponding second cache entry at a lower-level cache location.

SYSTEM COHERENCY PROTOCOL (17657830)

Inventor Vesselina PAPAZOVA

Brief explanation

The abstract describes a coherency protocol for a distributed computing system with multiple boards and processors. When a core on a processor needs data that is not in its cache, it first checks the caches of other cores on the same processor. If the data is not found, the processor can broadcast a request to other processors on the same board. If the data is still not found, the request is broadcasted to other boards in the system. The processors in those boards then search their caches for the data.

Abstract

Embodiments herein described a coherency protocol for a distributed computing topology that permits for large stalls on various interfaces. In one embodiment, the computing topology includes multiple boards which each contain multiple processors. When a particular core on a processor wants access to data that is not currently stored in its cache, the core can first initiate a request to search for the cache line in the caches for other cores on the same processor. If the cache line is not found, the cache coherency protocol permits the processor to then broadcast a request to the other processors on the same board. If a processor on the same board does not have the data, the processor can then broadcast the request to the other boards in the system. The processors in those boards can then search their caches to identify the data.

MULTIPROCESSOR SYSTEM CACHE MANAGEMENT WITH NON-AUTHORITY DESIGNATION (17657169)

Inventor Jason D. Kohl

Brief explanation

The abstract describes a system where a primary controller manages a cache line for a fetch request. The primary controller also handles a separate cache line request from a different entity. A secondary controller, associated with this different entity, is given authority over the cache line and manages multiple subsequent requests for the cache line from other entities. The secondary controller grants read-only access to these other entities and passes a non-authority token to each of them. In simpler terms, this system allows for efficient management of cache line requests from different entities by granting them limited access and passing tokens to ensure proper control.

Abstract

A primary controller has authority of a cache line associated with a fetch and manages a second cache line request from a different and non-associated secondary requesting entity. A secondary controller, associated with the secondary requesting entity, is granted authority of the cache line and further manages multiple subsequent simultaneous or overlapping requests for the cache line from different non-associated subsequent requesting entities by maintaining authority of the cache line, by granting read-only access to the cache line to respective subsequent controllers, each associated with a different subsequent requesting entity, and by passing a non-authority token to each of the respective subsequent controllers.

HOT LINE FAIRNESS MECHANISM FAVORING SOFTWARE FORWARD PROGRESS (17713263)

Inventor Gregory William Alexander

Brief explanation

The abstract describes a computer method that determines whether a request should be rejected. If rejection is required, the method further determines whether the request is likely to make progress in the software or not. Based on this determination, the method executes a random decision to either set or not set the requested state of the request. Finally, the request is rejected after the second random decision is executed.

Abstract

A computer-implemented method is provided. The method includes determining whether a rejection of a request is required and determining whether the request is software forward progress (SFP)-likely or SFP-unlikely upon determining that the rejection of the request is required. The method also includes executing a first pseudo random decision to set or not set a requested state of the request in an event the request is SFP-likely or SFP-unlikely, respectively, and rejecting the request following execution of the second pseudo random decision.

DECENTRALIZED HOT CACHE LINE TRACKING FAIRNESS MECHANISM (17713264)

Inventor Tu-An T. Nguyen

Brief explanation

This abstract describes a decentralized hot cache line tracking fairness mechanism. When a request is received to access a cache line, a decision is made to allow access based on the requested state and the current state of the cache line. If access is granted, the requested state, current state, and data of the cache line are transferred.

Abstract

Embodiments are for using a decentralized hot cache line tracking fairness mechanism. In response to receiving an incoming request to access a cache line, a determination is made to grant access to the cache line based on a requested state and a serviced state used for maintaining the cache line, a structure comprising the requested and serviced states. In response to the determination to grant access to the cache line, the requested state and the serviced state are transferred along with data of the cache line.

CASTOUT HANDLING IN A DISTRIBUTED CACHE TOPOLOGY (17708785)

Inventor ROBERT J. SONNELITTER, III

Brief explanation

The abstract describes a method for managing cache misses in a distributed cache system. When a cache miss occurs in one cache, that cache sends a message to all other caches in the system. The message includes information about the cache address that caused the miss and the cache line that needs to be evicted.

Abstract

Castout handling in a distributed cache topology, including: detecting, by a first cache of a plurality of caches, a cache miss; providing, by the first cache to each other cache of the plurality of caches, a message comprising: data indicating a cache address corresponding to the cache miss; and data indicating a cache line to be evicted.

DYNAMIC SYSTEM RECONFIGURATION BY PARTITION (17657960)

Inventor Tobias Huschle

Brief explanation

The abstract describes a computer-based approach to optimizing the reconfiguration of a dynamic system. The computer receives the current system configuration and a desired target configuration from a system administrator. It then determines the necessary actions to transform the current configuration to the target configuration. 

To organize these actions, the computer generates a dependency graph and divides it based on logical partitions. It also sorts the actions based on their dependencies and orders them according to the priority of each logical partition.

The computer then runs a simulation of the actions for each logical partition and finally performs the actions to reconfigure the system accordingly.

Abstract

In an approach to optimizing dynamic system reconfiguration, a computer receives an active system configuration and a target system configuration from a system administrator, where the target system configuration includes two or more logical partitions. A computer determines one or more reconfiguration actions required to transform the active system configuration to the target system configuration. A computer generates a dependency graph based on the determined reconfiguration actions. A computer divides the dependency graph along the two or more logical partitions. A computer sorts the determined reconfiguration actions by associated dependencies. A computer orders the determined reconfiguration actions based on a priority of each of the two or more logical partitions. A computer runs a first simulation of the determined reconfiguration actions for each of the two or more logical partitions. A computer performs the determined reconfiguration actions for each of the two or more logical partitions.

STORAGE DRIVER FOR MANAGING A MULTIPLE LAYER FILE SYSTEM ON THE CLOUD (17656882)

Inventor Jin Chi He

Brief explanation

The abstract describes the development of a storage driver for a cloud-based computing server, specifically for containerized servers. This storage driver is designed to organize and manage a multiple layer file system within the containers. It also aims to enhance the security of the containers and establish a fixed configuration for the file system stored within them.

Abstract

Creating a storage driver that is structured and configured to organize and operate a multiple layer file system on a cloud-based computing server, and more particularly to a containerized computing server. Additionally, the storage driver is used to improve the security of the containers and to define a static configuration of the multiple layer file system that is stored within the containers.

DATABASE QUERY MANAGEMENT USING A NEW COLUMN TYPE (17708202)

Inventor Sheng Yan SUN

Brief explanation

This abstract describes a computer method that involves collecting information about a database's activities and structure. The method then identifies related columns in the database and determines the appropriate data types for transferring these columns. It generates a "super union" column based on this information and the identified related columns. Finally, it updates the database by adding the super union column.

Abstract

A computer-implemented method includes: collecting, by a computing device, database activities and database structure information of a database; identifying, by the computing device, related columns in the database; determining, by the computing device, one or more data types for column transference of the identified related columns; generating, by the computing device, a super union column based on the column transference and the identified related columns; and updating, by the computing device, the database with the super union column.

UTILIZING A STRUCTURED AUDIT LOG FOR IMPROVING ACCURACY AND EFFICIENCY OF DATABASE AUDITING (17708440)

Inventor Jia Tian Zhong

Brief explanation

This abstract describes a computer-based method, system, and program for improving the accuracy and efficiency of auditing databases. It involves analyzing a database's table, list, or index to identify metadata, such as time series data, user data, IP addresses, and operation data. This metadata is then associated with the corresponding record or row from which it was extracted. Based on the data operation, a decision is made on whether to record a raw data image associated with the analyzed record or row. The identified metadata and recorded data images, if any, are stored in a structured audit log. When auditing information is needed, it can be obtained from the audit log by matching the query's record or row identifier with the one in the audit log.

Abstract

A computer-implemented method, system and computer program product for improving accuracy and efficiency of auditing databases. A table, list or index of a database is analyzed to identify metadata, which includes time series data, user data, an Internet Protocol address and operation data. The identified metadata is associated with the corresponding record or row of the table, list or index from which the metadata was extracted. A determination is then made as to whether to record a raw data image associated with the record or row of the analyzed table, list or index based on the corresponding data operation. The identified metadata as well as the recorded data images, if any, are stored in a structured audit log. Auditing information is then obtained from a structured audit log based on matching the record or row identifier (RID) associated with the query with the RID associated with the structured audit log.

AUTOMATED PARTITIONING OF A DISTRIBUTED DATABASE SYSTEM (17709802)

Inventor Hong Mei Zhang

Brief explanation

The abstract describes a method for creating a partition schema for a distributed database based on historical usage data. The partition schema determines how the data is divided and stored across multiple nodes in the database. The method also involves generating a unique identifier for each partition using a hash function and a weight value. The performance of the database is continuously monitored, and if it fails to meet a certain threshold, a redistribution procedure is initiated. This procedure involves changing the identifier of a partition by replacing the original weight value with a new one.

Abstract

An embodiment includes generating a partition schema for a distributed database based on historical usage data indicative of usage of the distributed database, where the generating of the partition schema comprises determining a partition range of a partition of the partition schema. The embodiment also includes generating a node identifier for the partition using a hash function and a first weight value assigned to the partition. The embodiment also includes monitoring performance data indicative of a performance of the distributed database, the monitoring comprising detecting a failure of the performance to satisfy a performance threshold. The embodiment also includes initiating, responsive to detecting the failure, a redistribution procedure by changing the node identifier of the partition by replacing the first weight value with a second weight value.

BIDIRECTIONAL DATA REPLICATION WITH WAIT FOR DATA FUNCTION (17657155)

Inventor Vassil Radkov Dimov

Brief explanation

This abstract describes a method where a processor receives a request to manipulate data in a specific database. The processor then sends this request to another database, known as the source database. The source database tries to save the requested data manipulation action. If it is successful, it sends the position of this action to a data replication engine. The processor then replicates the original data manipulation request in the target database, triggering the same action. Finally, the processor confirms to the target database that the data manipulation action has been completed successfully.

Abstract

In an approach, a processor receives a data manipulation request on a target database. A processor sends the data manipulation request to a source database. The source database attempts to persist a data manipulation action relating to the data manipulation request. Responsive to a successful attempt to persist the data manipulation action: the source database sends a log position of the data manipulation action to a data replication engine; a processor replicates the data manipulation request triggering the data manipulation action in the target database; and a processor confirms to the target database that the data manipulation action in the target database has been completed.

TECHNOLOGY FOR USING A SIMULATED STATE OF A DIGITAL TWIN AS A PASSWORD (17657149)

Inventor Devang Dineshchandra PATEL

Brief explanation

The abstract describes a method for authenticating access to a system. It involves creating a digital twin for each user, allowing them to make modifications to it. The digital twin then generates a value based on these modifications. The user is authenticated by comparing this generated value to a stored value. If they match, access to the system is granted. The abstract also mentions that a new password can affect a selected digital twin, and the resulting state is transformed using a hashing algorithm to generate the final password, known only to the service provider.

Abstract

Authenticating access to a system through the following operations: (i) determining at least one digital twin corresponding to a user; (ii) setting, by the user, modifications to at least one digital twin; (iii) generating, by the digital twin, a value based on the modifications; (iv) authenticating the user based on the generated value matching a stored value; and (v) based on the authentication, granting access to the system. A digital twin of a complex entity can have innumerable states based on the input values. In some embodiments, a new password can make an effect on a selected digital twin with one input or a sequence of inputs. The resulting state is transformed using a hashing algorithm to generate the final password, which is known only to the service provider, can act as a password.

SOFTWARE DISCOVERY WITHIN SOFTWARE PACKAGING AND DEPLOYMENT SYSTEMS (17706714)

Inventor Grzegorz Piotr Szczepanik

Brief explanation

This abstract describes a computer-based method for detecting software on a computer system. The method involves scanning the file systems on the computer and looking for specific signatures. If a signature is found, a plugin is selected based on the signature. The plugin is then used to query the operating environment of the file system for data that indicates what software is running. Based on this data, the method determines what software is running on the computer system.

Abstract

A computer-implemented method for software detection is disclosed. The computer-implemented method includes scanning a list of file systems present on a computer system and described by a respective mount point for a signature from a set of predetermined signatures. The computer-implemented method further includes responsive to detecting the signature from the set of predetermined signatures, selecting a particular plugin from a predetermined list of plugins based, at least in part, on the detected signature. The computer-implemented method further includes querying, using the plug-in, an operating environment of the filesystem for data indicative of software running in the operating environment. The computer-implemented method further includes determining software running in the operating environment based, at least in part, on the data returned from querying the operating environment of the filesystem.

DYNAMICALLY BLOCKING CREDENTIAL ATTACKS USING IDENTITY INTELLIGENCE (17706707)

Inventor Bruno dos Santos Silva

Brief explanation

This abstract describes a computer system and method for preventing credential attacks. It receives authentication transactions with various features, such as source IP, username, and password. These features are then clustered together using a set of rules. For example, transactions from the same IP or targeting the same username or password are grouped together. If a cluster is determined to be malicious, it is classified as such, otherwise, it is classified as non-malicious. The system can also block certain activities based on the features of a malicious cluster.

Abstract

A computer-implemented apparatus and related method prevent credential attacks. The method receives authentication transactions (ATs) comprising AT features (ATFs). The method then performs clustering, to produce clustered ATFs (CATFs) from the ATFs utilizing rule-based clustering. The clustering may operate by assigning user credentials: 1) from a same source IP to a common CATF; 2) targeting a same username to a common CATF; and/or with a same password to a common CATF. Upon determining a CATF is malicious, the method may classify the CATFs as malicious, and otherwise, classify the CATF as non-malicious. The method may further block an activity using a feature included in a malicious CATF.

ARCHITECTURE AGNOSTIC SOFTWARE-GENOME EXTRACTION FOR MALWARE DETECTION (17708415)

Inventor Dhilung Kirat

Brief explanation

The abstract describes a method for detecting malware in software code. The method involves analyzing the code at the IR level and converting it into a canonical representation. This allows for the extraction of features that can be used to create similarity representations. These representations are then compared to known malware to identify any malicious software. The approach can be used for both malicious and benign software.

Abstract

An approach for detection of malware is disclosed. The approach involves the use of using IR level analysis and embedding of canonical representation on a suspecting sample of software code. The approach can be applied to both malicious and benign software. Specifically, the approach includes converting a binary code to an IR (intermediate representation), canonicalizing the IR into a canonical IR, extracting one or more similarity representation based on the extracted features and comparing the one or more similarity representation to known malware.

USING SMART CONTRACTS TO MANAGE HYPER PROTECT DATABASE AS A SERVICE (17656673)

Inventor Peng Hui Jiang

Brief explanation

This abstract discusses the use of a smart contract to address the issue of isolation between database users and service operators in a hyper-protect database as a service (DBaaS) environment. The smart contract enables the service operator to perform operations on sensitive and secure data in a user's database without exposing the actual content of that data. This solution aims to enhance the security and privacy of the DBaaS system.

Abstract

Building and using a smart contract in order to resolve the isolation between database users and service operators for hyper-protect database as a service (DBaaS). The use of the smart contract in the hyper-protect DBaaS environment allows the service operator to perform operations on sensitive and secure data in the database owned by a user without necessarily revealing the content of the sensitive and secure data.

METHOD TO PRIVATELY DETERMINE DATA INTERSECTION (17707099)

Inventor Allon Adir

Brief explanation

The abstract describes a computer-based method for privately determining the intersection of data sets. The method involves comparing two sets of records to find identical records in a specific field. These identical records are then removed from each set to create two subsets. Locality sensitive hash values are computed separately for each subset, specifically for the records in the specific field. The method then performs a private set intersection between the computed hash values for the two subsets. Finally, the method determines if there are any matching pairs of records between the subsets based on a similarity score that exceeds a predetermined threshold.

Abstract

A computer-implemented method for privately determining data intersection is disclosed. The computer-implemented method includes performing private set intersection between two record sets to determine identical intersecting records corresponding to a particular record field. The computer-implemented method includes removing any identical intersecting records from each record set to form two record subsets. The computer-implemented method includes separately computing locality sensitive hash values for each of the two record subsets, wherein the locality sensitive hash values are computed for records corresponding to the particular record field. The computer-implemented method includes jointly performing private set intersection between the locality sensitive hash values separately computed for each of the two record subsets. The computer-implemented method further includes determining that an intersecting pair of records between the two record subsets are a match based, at least in part, on a similarity score associated with the intersecting pair of records being above a predetermined threshold.

EXTENDING ENCRYPTION TO PCIE LINKS (17706747)

Inventor Christopher J. Colonna

Brief explanation

This abstract describes a method for adding encryption to data transfer on PCIe links. The method involves receiving a list of encryption options, selecting one, and using it to encrypt the data without relying on encryption services from a Host Bus Adapter (HBA). The encrypted data is then directed to its destination.

Abstract

An approach for extending encryption to input/output (I/O) on Peripheral Component Interconnect express (PCIe) links. The approach receives a proposal list of available encryption mechanisms. The approach selects an encryption mechanism from the proposal list, the encryption mechanism performs the encryption without encryption services from an associated Host Bus Adapter (HBA). The approach directs the I/O to the encryption mechanism.

NEURAL NETWORK PREDICTIONS OF FLUID FLOW IN POROUS MEDIA (17708319)

Inventor Rodrigo Neumann Barros Ferreira

Brief explanation

This abstract describes a method for predicting the flow of fluids through porous materials. The method involves using a computer to access a representation of the capillary network within the material. From this representation, simplified network representations are generated. The computer then uses a simulator to determine the fluid flow properties of each simplified network representation. These properties are used to train a neural network model, which can then be used to predict the fluid flow properties of the porous material.

Abstract

Systems and methods for predicting fluid flow of porous media are provided. In implementations, a method includes: accessing, by a computing device, a capillary network representation of a porous medium sample; generating, by the computing device, a set of simplified network representations from the capillary network representation; determining, by the computing device, simulated fluid flow properties of each of the simplified network representations using a simulator to perform fluid flow simulations; and training, by the computing device, a neural network (NN) model utilizing the set of simplified network representations as inputs and the simulated fluid flow properties as model targets, thereby generating a trained NN model for predicting fluid flow properties of the porous medium.

FEED-FORWARD DESIGN OF THREE-DIMENSIONAL QUANTUM CHIPS (17657543)

Inventor Nicholas Anthony Lanzillo

Brief explanation

This abstract describes systems, methods, and computer program products that help in the design of three-dimensional quantum chips. The system includes a processor that executes computer executable components stored in memory. These components consist of an analysis component that analyzes the layout of a quantum chip and a modification component that makes changes to the layout of another quantum chip based on the analysis of the first layout.

Abstract

Systems, computer-implemented methods, and computer program products to facilitate feed-forward design of three-dimensional quantum chips are provided. According to an embodiment, a system can comprise a processor that executed computer executable components stored in memory. The computer executable components can comprise an analysis component that performs an analysis of a first layout of a first quantum chip. The computer executable components further comprise a modification component that modifies a second layout of a second quantum chip based on the analysis of the first layout.

CONTENT ASSOCIATION IN FILE EDITING (17657191)

Inventor Melita Saville

Brief explanation

The abstract describes a computer technology that helps with organizing and editing files. It involves analyzing changes made to a file currently being edited and examining the contents of other files. The technology identifies any other files that are related to the edited file by finding similarities between their contents and the changes made. It then makes corresponding changes to the related files.

Abstract

Computer technology for content association in file editing. The method includes providing one or more files including a first element currently being edited and including at least one other element of a different format to the first element. The method analyzes changes to the first element to obtain information relating to the changes and analyzing the contents of at least one other element. The method identifies any of the other elements that are correlated elements to the first element by determining an association between the contents of the other element and the changes of the first element and instigates a corresponding change to the contents of any correlated elements.

DETECTION AND CORRECTION OF MIS-TRANSLATION (17657402)

Inventor Takaaki Shiratori

Brief explanation

The abstract describes a method for improving machine translation results. It involves using a processor to receive a document in one language and translate it into another language using a neural machine translation model. The processor also uses a natural language understanding model to determine attribute values from the original and translated documents. These attribute values are then compared to calculate a score that indicates the quality of the translation.

Abstract

In a method for improving machine translation results, a processor receives a target document in a first language. A processor may also translate the target document into a first translated document in a second language using a first neural machine translation (NMT) model, determine a target attribute value from the target document and a first translated attribute value for the first translated document using a natural language understanding (NLU) model, and compare the target attribute value to the first translated attribute value to determine a first comparison score for the first NMT model.

MODIFIED DEEP LEARNING MODELS WITH DECISION TREE LAYERS (17657103)

Inventor Zhong Fang Yuan

Brief explanation

The abstract describes techniques for improving the efficiency of deep learning models in computing environments with limited floating point computation resources. The process involves training a deep learning model using a set of training data and recording input and output values from each layer of the trained model. These values are used to create deep forest decision tree models for each layer. Experimental versions of the trained model are then generated by replacing different layers with their corresponding deep forest decision tree models. These experimental versions are ranked based on their accuracy compared to the original trained model. Finally, an updated trained model is created by replacing one or more layers with their corresponding deep forest decision tree models.

Abstract

Disclosed are techniques for modifying deep learning models (such as neural networks) to run more efficiently in computing environments with limited floating point computation resources. A deep learning model is trained using a set of training data. Input and output values are then recorded from the layers of the trained model when supplied with the training data, which are then used to generate deep forest decision tree models corresponding to individual layers of the trained model. Experimental versions of the trained model are then generated with different layers of the trained model replaced with their corresponding deep forest decision tree models. These experimental versions are then ranked according to the accuracy of their results compared to the results of the trained model. An updated trained model is then generated with one or more layers replaced with their corresponding deep forest decision tree models.

TWO-DIMENSIONAL MESH FOR COMPUTE-IN-MEMORY ACCELERATOR ARCHITECTURE (17657431)

Inventor Shubham Jain

Brief explanation

The abstract describes a new architecture called compute in-memory (CIM) accelerator for deep neural networks (DNN). This architecture includes a first analog fabric engine that consists of multiple CIM analog tiles. Each CIM analog tile can store a matrix of weight operands and perform computations in-memory, producing outputs from inputs. The first analog fabric also includes compute cores and microcontrollers that execute instructions. On-chip interconnects connect all CIM analog tiles to the compute cores.

Abstract

Embodiments disclosed herein include a compute in-memory (CIM) accelerator architecture for deep neural network (DNN). The CIM accelerator architecture may include a first analog fabric engine having a plurality of compute in-memory (CIM) analog tiles. Each CIM analog tile may be configured to store a matrix of weight operands producing a vector of outputs from a vector of inputs, and perform in-memory computations. The first analog fabric may also include a plurality of compute cores. Each CIM analog tile and each compute core may include a microcontroller configured to execute a set of instructions. The first analog fabric may also include on-chip interconnects communicatively connecting all CIM analog tiles in the plurality of CIM analog tile to the compute cores.

Knowledge Graph Driven Content Generation (17709520)

Inventor Qian Pan

Brief explanation

This abstract describes a computer system, program, and method for managing knowledge graphs and datasets. It involves identifying new words from a virtual environment and using the virtual environment to understand their meaning. This understanding is then used to expand the dataset and knowledge graph.

Abstract

Embodiments are provided that related to a computer system, a computer program product, and a computer-implemented method for dynamically managing knowledge graphs and their corresponding datasets. Embodiments include identifying a neologism from a virtual environment, and leveraging a virtual environment exploration to resolve a meaning of the identified neologism. The resolved meaning of the neologism is applied to a dynamic expansion of a dataset and a corresponding knowledge graph.

REINFORCEMENT LEARNING STABILITY OPTIMIZATION (17706686)

Inventor Sathya Santhar

Brief explanation

This abstract describes a computer-based method for optimizing reinforcement learning. It involves determining the stability of a future state in a reinforcement learning problem. If the stability is below a certain threshold, an alternate future state's stability is evaluated. If the stability is above the threshold, the system transitions from the current state to the future state. The method aims to improve the efficiency and effectiveness of reinforcement learning algorithms.

Abstract

A computer-implemented method for optimizing reinforcement learning based on a stability of a reinforcement learning state is disclosed. The computer-implemented method includes determining whether a stability of a next reinforcement learning state of a reinforcement learning problem is above a predetermined threshold. The computer-implemented method further includes responsive to determining that the stability of the next reinforcement state is below the predetermined threshold, determining a stability of an alternate next reinforcement learning state of the reinforcement learning problem. The computer-implemented method further includes responsive to determining that the stability of the next reinforcement state is above the predetermined threshold, transitioning from a current reinforcement learning state to the next reinforcement learning state based, at least in part, on determining that the stability of the next reinforcement learning state is above the predetermined threshold.

CLASS-SPECIFIC PREDICTOR IMPORTANCE (17709646)

Inventor Lei Tian

Brief explanation

The abstract describes a method for determining the importance of a specific predictor indicator for a particular class in a machine learning model. This is done by creating a tree structure with nodes representing different class label subgroups and predictor indicators. The importance of the selected predictor indicator is calculated by combining its frequency and purity within each instance of the indicator in the tree structure. The resulting tree structure can be displayed in a graphical user interface, highlighting the paths that lead to the selected class label subgroup containing the indicator.

Abstract

Determining a class-specific predictor indicator importance can include generating, using machine learning, a prediction model having a tree structure including nodes, class label subgroups, and class-specific predictor indicators. A class-specific predictor indicator importance can be generated for a selected class-specific predictor indicator by merging a term predictor indicator frequency and a purity predictor indicator frequency at each instance of the selected class-specific predictor indicator within one or more nodes of the tree structure. A representation of the tree structure displayed in a graphical user interface can depict each path between a root node of the tree structure and a leaf node mapped to the selected class label subgroup having a node containing an instance of the selected class-specific predictor indicator in a manner that contrasts with other paths between the root node and other leaf nodes of the tree structure.

INTEGRATED MACHINE LEARNING PREDICTION AND OPTIMIZATION FOR DECISION-MAKING (17708834)

Inventor Dzung Tien Phan

Brief explanation

This abstract describes a method that involves training multiple machine learning models and using them to generate a solved optimization model. The trained models are then used to provide control input and predicted outputs based on the solved optimization model.

Abstract

A method includes training, by one or more processing devices, a plurality of machine learning predictive models, thereby generating a plurality of trained machine learning predictive models. The method further includes generating, by the one or more processing devices, a solved machine learning optimization model, based at least in part on the plurality of trained machine learning predictive models. The method further includes outputting, by the one or more processing devices, one or more control input and predicted outputs based at least in part on the solved machine learning optimization model.

FEATURE SEGMENTATION-BASED ENSEMBLE LEARNING FOR CLASSIFICATION AND REGRESSION (17709704)

Inventor Lei Tian

Brief explanation

The abstract describes a method for creating a feature segment-based ensemble. This involves analyzing a set of training data to identify strongly and weakly correlated features. For each strongly correlated feature, a separate training set is created. Machine learning algorithms are then applied to these training sets to create multiple models. The models that improve the accuracy of the ensemble are integrated into the final feature segment-based ensemble.

Abstract

Constructing a feature segment-based ensemble can include generating a data structure for each element of an initial set of training data. Multiple strongly correlated features of the elements can be identified as well as weakly correlated features. For each strongly correlated feature, a feature segmentation training set can be generated, each training set's elements each containing one of the strongly correlated features and excluding other strongly correlated features. One or more machine learning algorithms can be selected from a software library. The one or more machine learning algorithms can be applied to the feature segmentation training sets to train multiple machine learning models. Each machine learning model that improves the predictive accuracy of the feature segment-based ensemble can be integrated in the feature segment-based ensemble.

AUTOMATED COMPLIANCE BENCHMARK MANAGEMENT (17657179)

Inventor Anthony Erwin

Brief explanation

The abstract describes a request to create a system that automatically checks if an organization is following industry and internal regulations. A neural network will analyze the regulations and the organization's existing record-keeping and data processing systems. It will then create benchmarks based on this analysis to determine if the organization is compliant or not. These benchmarks will be tested by a compliance system to provide an objective verification of the organization's compliance status.

Abstract

A request to generate an automated compliance verification framework for an organization is received. A neural network analyzes industry and internal regulations of the organization, as well as existing record-keeping and data processing applications of the organization. The neural network determines a set of benchmarks derived from existing variables from the record-keeping and data processing applications to objectively verify compliance or non-compliance with the industry and internal regulations. The neural network determines these benchmarks by comparing data of the record-keeping and data processing applications against the industry and internal regulations. A compliance system is caused to execute an automated test of each of the set of benchmarks verifying whether the organization is objectively in compliance with the industry and internal regulations.

WORKFLOW TRANSFORMATION FRAMEWORK (17656917)

Inventor Vasileios Vasileiadis

Brief explanation

This abstract describes an approach for transforming workflows based on goals and constraints. A processor receives a workflow definition and events from a workflow orchestrator. The events can be parsing events or scheduling events. The processor uses transformers to determine transformations to the workflow based on a set of goals and constraints. These transformations can include adding new nodes or graphs, modifying existing nodes or graphs, or removing existing nodes or graphs. The processor then applies these transformations dynamically using enforcers based on the set of goals and constraints.

Abstract

In an approach for transforming workflows based on goals and constraints, a processor receives a workflow definition and one or more events for a workflow output by a workflow orchestrator, wherein the one or more events are at least one of a parsing event and a scheduling event. A processor determines, using one or more transformers, one or more transformations to the workflow based on a set of goals and constraints, wherein the one or more transformations is at least one of addition of a new node, addition of a new graph, modification of at least one existing node, modification of at least one existing graph, removal of at least one existing node, and removal of at least one existing graph. A processor dynamically applies, using one or more enforcers, the one or more transformations to the workflow based on the set of goals and constraints.

INCENTIVE-BASED REROUTING OF ITEM DELIVERY (17700843)

Inventor Shikhar Kwatra

Brief explanation

The abstract describes a system where a first user has ordered an item for delivery to a specific location. While the item is being delivered, a second user also orders the same item and requests expedited delivery. The system offers the first user an incentive to agree to a delayed delivery of their item. At the same time, the system offers the second user the option of expedited delivery in exchange for additional payment. If both users accept these offers, the system changes the delivery location of the item to the second user while it is still en-route.

Abstract

A delivery location of a first user is linked to a tokenized identifier of a package including an ordered item and delivery is initiated. A second order for the same item is received from a second user also requesting expedited delivery while the item ordered by the first user is en-route for delivery. An incentive is offered to a computing device of the first user in exchange for agreeing to a delayed delivery of the item ordered by the first user. An expedited delivery timeframe in exchange for additional compensation is offered to a computing device of the second user, and in response to receiving an acceptance of the incentive for delayed delivery and the expedited delivery in exchange for additional compensation the link to the tokenized identifier is changed to a delivery location of the second user while the package including the item is en-route.

INTELLIGENT SUPPLY CHAIN OPTIMIZATION (17657047)

Inventor Rahul NAIR

Brief explanation

The abstract describes a system that uses intelligent classification to identify the origin and history of a product. It explains that the system can receive a request for a transaction agreement from a user and then generate a revised request based on various factors such as user profiles, feedback from multiple parties, constraints related to the request, and the fulfillment requirements of the entity involved in the transaction.

Abstract

Intelligent classification for product pedigree identification are presented. A transaction agreement request may be received from a user. A revised transaction agreement request may be generated based on one or more user profiles, a multi-party entity feedback loop, one or more constraints relating to the transaction agreement request, and a transaction agreement fulfillment requirements of the entity.

GENERATING PRODUCT RECOMMENDATIONS USING STACKED MACHINE LEARNING MODELS (17656966)

Inventor Stephen Carrow

Brief explanation

This abstract describes a method, computer system, and computer program for generating recommendations using stacked models. The system receives two datasets - one related to a territory plan and the other related to prospective-based data. It then identifies multiple target variables associated with a B2B party in these datasets. The system determines the convergence of at least two target variables and generates a product recommendation based on this convergence.

Abstract

A method, computer system, and a computer program for generating recommendations using stacked models is provided. The present invention may include receiving a first dataset pertaining to a territory plan associated with a user and a second dataset pertaining to prospective-based data. The present invention may then include detecting a plurality of target variables associated with the B2B party within the first and second datasets. The present invention may further include determining a convergence of at least two target variables of the plurality of target variables. The present invention may further include generating a product recommendation associated with the B2B party based on the convergence.

DIGITAL AND PHYSICAL EXPERIENCE CORRELATION FOR PRODUCT RECOMMENDATION (17709537)

Inventor Kavitha Hassan Yogaraj

Brief explanation

The abstract describes a system that uses digital twin models of a user, a location, an event venue, and clothing items to generate personalized product recommendations for the user's planned event at the venue. It also generates a visual depiction of the recommended product being worn by the user at the event. The system is able to answer natural language queries about the product recommendation depiction.

Abstract

Using a digital twin model of a user, a digital twin model of a geographical location, a digital twin model of an event venue located at the geographical location, and a plurality of digital twin models of clothing items, a product recommendation customized to the user and a planned event is generated, the planned event planned to occur at the event venue. A product recommendation depiction is generated, the product recommendation depiction comprising a depiction of the product recommendation being worn by the user at the planned event. An answer to a natural language query regarding the product recommendation depiction is generated.

REDUCING ECONOMIC LOSS DUE TO TRAFFIC INCIDENTS BY PROPOSING ACTIONS (17657394)

Inventor Mitsuru Chinen

Brief explanation

This abstract describes an approach to reduce economic loss caused by traffic events. It involves a processor that receives information from transportation service providers about a traffic event. The processor then analyzes this information to identify the affected area and users. It gathers information about each affected user and prioritizes them. Based on this information and priority, the processor determines alternative plans for each user and proposes them as solutions to the traffic event.

Abstract

In an approach for reducing economic loss due to traffic events, a processor receives a set of transportation operation information from one or more transportation service providers about a traffic event. A processor analyzes the set of transportation operation information to identify an area affected by the traffic event and one or more users affected by the traffic event. A processor gathers a set of information about each user of the one or more users affected by the traffic event. A processor prioritizes the one or more users affected by the traffic event. A processor determines an alternative plan for each user of the one or more users affected by the traffic event based on the set of information and a priority number given to each user. A processor proposes the alternative plan to each user of the one or more users affected by the traffic event.

COGNITIVE FRAMEWORK FOR IDENTIFICATION OF QUESTIONS AND ANSWERS (17654873)

Inventor Pinaki Bhattacharya

Brief explanation

This abstract describes a computer-based method that uses previous learning and user evaluation to generate personalized questions and answers from a dataset. The method involves creating a library of potential questions and answers based on the user's previous learning and evaluation score. It then uses sentence-based machine translation and natural language processing tools to generate personalized questions for the user related to the dataset. The method also identifies multiple answers for these personalized questions based on the information available in the dataset. Finally, it provides these answers to the user for verification and evaluation.

Abstract

A computer-implemented method for providing a framework to identify questions and answers dynamically from a dataset based on previous learning and an evaluation score of a user. The method includes creating a library of potential questions and answers from the dataset based on the previous learning and evaluation score of the user, and generating a set of personalized questions, for the user, related to the dataset by utilizing sentence-based machine translation (SBMT) and natural language processing (NLP) tools. The method further includes identifying a plurality of answers for the set of personalized questions for the user, based on collective information available in the dataset, and providing, to the user, the plurality of answers for the set of personalized questions for verification and evaluation.

OPPORTUNISTIC CLUES IN MULTIPLE-CHOICE TEST QUESTION EVALUATION SYSTEMS (17657170)

Inventor Jennifer L. Szkatulski

Brief explanation

This abstract describes a method for creating personalized clues for multiple-choice test questions. The method involves analyzing the questions to identify the concepts needed to answer them correctly. A dependency graph is generated for each question, and the user's answers are monitored. If the user answers a question incorrectly, a known concept database is created for them. When the user moves on to a second question, personalized clues are generated based on the dependency graph and the known concept database. These clues are then presented to the user to help them answer the question correctly.

Abstract

In an approach for generating personalized clues for multiple-choice test questions, a processor analyzes one or more multiple-choice test questions to identify one or more concepts required to be understood to correctly answer each multiple-choice test question. A processor generates a dependency graph corresponding to each multiple-choice test question. A processor monitors a user answer the one or more multiple-choice test questions. Responsive to the user answering at least one of the one or more multiple-choice test questions, a processor assesses whether the user answered the at least one of the one or more multiple-choice test questions correctly. A processor generates a known concept database for the user. Responsive to determining the user is answering a second multiple-choice test question, a processor generates at least one personalized clue based on the dependency graph and the known concept database. A processor presents the user with the at least one personalized clue.

CONTEXT AWARE SPEECH TRANSCRIPTION (17695886)

Inventor HIROKI NAKANO

Brief explanation

The abstract describes a method for context aware speech transcription. It involves obtaining a collection of spoken words for a specific field, and then editing any incorrectly used words to create a corrected version. Training sets are created using both the original and corrected versions of the spoken words. The method also determines the best percentage of training sets to use in order to accurately transcribe speech related to the specific field.

Abstract

The present inventive concept provided for context aware speech transcription. The method includes obtaining speech corpora for a target domain. A corrected speech corpora is created by editing misused words in the speech corpora with correct words for the target domain. The training sets are prepared based on the speech corpora and corrected speech corpora, and an optimal percentage of the training sets to use for accurate transcription of speech related to the target domain is determined.

MAGNETIC RECORDING TAPE AND APPARATUS (17648758)

Inventor MARK ALFRED LANTZ

Brief explanation

The abstract describes a type of magnetic recording tape that is used for storing data. The tape consists of several layers, including a tape substrate, a perpendicular magnetic recording layer, and a soft-magnetic underlayer. The perpendicular magnetic recording layer contains magnetic particles suspended in a binder material, while the soft-magnetic underlayer is made of a continuous film of soft-magnetic material. The magnetic particles in the recording layer can be made of different materials such as barium ferrite, strontium ferrite, epsilon iron oxide, or chromium dioxide. The abstract also mentions a tape storage apparatus that includes a read/write head for writing data on the magnetic tape, a reel of the magnetic tape described above, and a mechanism for transporting the tape past the read/write head.

Abstract

A magnetic recording tape comprises a tape substrate, a perpendicular magnetic recording layer disposed over the tape substrate, and a soft-magnetic underlayer disposed between the recording layer and the tape substrate. The perpendicular magnetic recording layer comprises magnetic particles suspended in a binder material, and the soft-magnetic underlayer comprises a continuous film of soft-magnetic material. The magnetic particles in the recording layer comprise one of barium ferrite, strontium ferrite, epsilon iron oxide and chromium dioxide. Tape storage apparatus employing such tape is also provided. The apparatus comprises a read/write head having at least one probe write-head for writing data by perpendicular recording on magnetic tape, at least one reel of magnetic tape as defined above, and a tape transport mechanism for transporting the magnetic tape past the read/write head.

DUAL CHIP CLOCK SYNCHRONIZATION (17657520)

Inventor Hagen Schmidt

Brief explanation

This abstract describes a method for synchronizing the clocks of two semiconductor circuits. Initially, both circuits are operating at a slow clock speed that allows for the proper functioning of an input/output interface between them. The division counters of the clocks are synchronized at this slow speed. 

Then, the circuits are switched to a faster clock speed, which is a multiple of the slow speed. However, at this fast speed, the input/output interface is not capable of operating.

To maintain synchronization between the two circuits at the fast clock speed, pulses from the division counter of the first circuit are sent to a spare division counter of the second circuit. The primary division counter of the second circuit is then aligned to this spare division counter, ensuring that both circuits remain synchronized at the fast clock speed.

Abstract

Clocks of two semiconductor circuit are set to a common clock source when both the first and second semiconductor circuits are in a slow clock speed at which an input/output (TO) at an interface between the first and second semiconductor circuit is capable of operating. Division counters of the two clocks are synchronized at the slow clock speed. The two semiconductor circuits are switched to a fast clock speed that is a multiple of the slow speed, wherein the IO is not capable of operating at the fast clock speed. Pulses from a division counter of the first circuit are sent to a spare division counter of the second circuit, and then a primary division counter of the second counter is aligned to this spare division counter to keep the two circuits synchronized at the fast clock speed.

TETRAGONAL HALF METALLIC HALF-HEUSLER COMPOUNDS (17710399)

Inventor SERGEY FALEEV

RECONFIGURABLE DATA PROCESSING AND STORAGE UNIT FOR DEEP NEURAL NETWORKS (17709794)

Inventor Rajiv Joshi

Brief explanation

The abstract describes an apparatus that includes a memory array with multiple word lines, bit line pairs, and memory cells. The memory cells are connected to the word lines and bit line pairs at various locations. The apparatus also includes word line drivers, a dynamic voltage boost, and a controller. The controller is responsible for activating the dynamic voltage boost to enhance the performance of the cells during a multiply accumulate operation.

Abstract

An apparatus includes a memory array. The array in turn includes a plurality of word lines, a plurality of bit line pairs intersecting the plurality of word lines at a plurality of cell locations, and a plurality of memory cells, coupled to the plurality of word lines and the plurality of bit line pairs, and located at the plurality of cell locations. A plurality of word line drivers are coupled to the plurality of word lines, a dynamic voltage boost is coupled to the memory array, and a controller is coupled to the plurality of word line drivers and the dynamic voltage boost. The controller is configured to cause the dynamic voltage boost to boost the cells during a multiply accumulate operation.

DEVICE FOR MATRIX-VECTOR MULTIPLICATIONS (17706695)

Inventor Ghazi Sarwat Syed

Brief explanation

The invention is about a device that can multiply a matrix with a vector. It uses a memory crossbar array with row lines, column lines, and junctions. Each junction has a programmable resistive element and an access element. The device also has a readout circuit that performs read operations by applying positive and negative read voltages of different amplitudes. This helps correct polarity dependent current asymmetricities.

Abstract

The invention is notably directed to a device for performing a matrix-vector multiplication of a matrix with a vector. The device comprises a memory crossbar array comprising a plurality of row lines, a plurality of column lines and a plurality of junctions arranged between the plurality of row lines and the plurality of column lines. Each junction comprises a programmable resistive element and an access element for accessing the programmable resistive element. The device further comprises a readout circuit configured to perform read operations by applying positive read voltages of one or more first amplitudes and negative read voltages of one or more second amplitudes corresponding to the one or more first amplitudes. The one or more first amplitudes and the corresponding one or more second amplitudes are different from each other, thereby correcting polarity dependent current asymmetricities.

EFFECTIVE MOBILITY (17656984)

Inventor Pritish Ranjan Parida

Brief explanation

This abstract describes a method, computer system, and computer program for effectively scoring the mobility of a user. The system receives acceleration data from the user and uses it to determine the user's activity state. It then records the amount of time spent in each activity state. Finally, it calculates an effective mobility score for the user based on a weighted sum of the time spent in each activity state within a specified time period.

Abstract

A method, computer system, and a computer program product for effective mobility scoring is provided. The present invention may include receiving an acceleration data associated with a user. The present invention may also include determining a respective activity state of a plurality of activity states for the user based on the received acceleration data. The present invention may also include recording an amount of time spent in a respective activity state of a plurality of activity states. The present invention may further include determining an effective mobility score of the user for a specified time-window based on calculating a weighted sum of time spent in the plurality of activity states.

CELL OPTIMIZATION THROUGH SOURCE RESISTANCE IMPROVEMENT (17657304)

Inventor David WOLPERT

Brief explanation

The abstract describes a method and structures for using shared sources in semiconductor devices, specifically in very-large-scale integration (VLSI) devices. By sharing the source, the current passing through the device is increased, leading to improved device performance. This can result in benefits such as reduced delay in the device and associated logic paths, as well as improved power efficiency. The method involves implementing these shared sources during the design process of a semiconductor device.

Abstract

Method and structures for shared (dual) sources for a single device in semiconductor devices such as very-large-scale integration (VLSI) devices. The shared-source improves or increases a current that passes through the device (e.g., to a drain region associated with the shared-source), which in turn increases a performance of the device. Example improvements may include a delay improvement of the device and associated logic paths and/or a power improvement for the device. The method includes operations for design improvements during a design process by implementing shared-sources in a semiconductor device design.

VERTICALLY-STACKED FIELD EFFECT TRANSISTOR CELL (17657378)

Inventor Albert M Chu

Brief explanation

The abstract describes a system that consists of multiple tracks. One of the tracks has a power rail for a specific voltage. Below the power rail, there is a via, which is a conductive path, in electrical contact with the power rail. Beneath the via, there is a contact point, also in electrical contact with the via. Below the contact point, there is a field effect transistor (FET), which is a type of electronic device, isolated from the contact point. Another FET is present below the first FET and in electrical contact with it. Below the second FET, there is another contact point, in electrical contact with the second FET. Below this contact point, there is another via, in electrical contact with the contact point. Finally, there is a buried power rail (BPR) below the second via, which is in electrical contact with it and operates at a different voltage than the power rail on the first track.

Abstract

Embodiments are disclosed for a system. The system includes multiple tracks. Further, one track includes a power rail for a first voltage. The system also includes a first via, disposed beneath, and in electrical contact with, the power rail. The system additionally includes a first contact, beneath, and in electrical contact with, the first via. The system further includes a first field effect transistor (FET), beneath, and in electrical isolation with, the first contact. Additionally, the system includes a second FET, beneath, and in electrical contact with, the first FET. Further, the system includes a second contact, beneath, and in electrical contact with, the second FET. Also, the system includes a second via, beneath, and in electrical contact with, the second contact. The system additionally includes a buried power rail (BPR), beneath, and in electrical contact with, the second via, wherein the BPR comprises a second voltage.

FINE-PITCH JOINING PAD STRUCTURE (17657162)

Inventor Toyohiro Aoki

Brief explanation

This abstract describes a semiconductor device that consists of two integrated circuit (IC) chips. The first chip has a substrate and a spacer connected to it, which contains holes. Some of these holes have a specific shape, and solder bumps are placed in these holes. The second chip also has a substrate, and it has electrode pads that extend from the substrate and are connected to the solder bumps. One or more of these electrode pads have a different shape than the corresponding solder bumps. When the shapes of the solder bumps and electrode pads are projected onto each other, there is a gap between them.

Abstract

A semiconductor device includes two integrated circuit (IC) chips. The first IC chip includes substrate, a spacer connected to the substrate and including holes, wherein at least one of the holes has a first shape, and solder bumps positioned in the holes, respectively. The second IC chip includes a substrate, electrode pads extending from the substrate and connected to the solder bumps, respectively. At least one of the electrode pads that corresponds to the at least one of the solder bumps has a second shape, and the first shape and the second shape are non-coextensive such that there is at least one gap between the first shape and the second shape when projected on each other.

ARCHITECTURE AND DEVICE USING OPTICAL ELEMENT AND COMPUTER CHIP FOR OPTICAL SIGNAL TRANSMISSION (17657767)

Inventor Frank Robert Libsch

Brief explanation

This abstract describes a device and method that use an optical element (OE) for both electrical and optical communications. The device includes a substrate with a wiring layer that has an optically transparent path, allowing optical signals to pass through. An optical coupling layer is connected to the wiring layer and has micro-lenses that focus or collimate the optical signals through the transparent path. The OE is connected to the wiring layer and is positioned in alignment with the transparent path to communicate optical signals. One or more semiconductor chips can be connected to the OE to control it.

Abstract

A device and associated method include using an optical element (OE) for electrical and optical communications on the device. A substrate includes a wiring layer with an optically transparent path which allows optical signals to pass therethrough. An optical coupling layer is coupled to the wiring layer, and the optical coupling layer includes at least one micro-lens for focusing or collimating the optical signals through the transparent path. An OE is coupled to the wiring layer, and the OE is positioned in optical alignment with the optically transparent path for communicating optical signals. One or more semiconductor chips can be communicatively coupled to an OE for controlling the OE.

SIZE-EFFICIENT MITIGATION OF LATCHUP AND LATCHUP PROPAGATION (17703092)

Inventor Terence Hook

Brief explanation

The abstract describes a set of transistor elements that are used in electronic devices. These elements are made up of a substrate, which is a base material, and two wells that are formed on the substrate. The wells are of a different doping type than the substrate, meaning they have a different concentration of impurities. 

The set of transistor elements also includes two complementary transistor cells, which are used to create complementary logic circuits. Complementary transistors are made up of both n-type and p-type transistors, which work together to perform logic operations.

Additionally, there is an anti-propagation region between the two wells. This region is of the same doping type as the substrate and helps prevent unwanted electrical signals from propagating between the two wells.

Overall, this abstract describes the basic structure and components of a set of transistor elements used in electronic devices.

Abstract

A set of transistor elements includes a substrate of a first doping type and a first well and a second well, both of a second doping type and both formed on the substrate. The set of transistor elements also includes a first complementary transistor cell and a second complementary transistor cell. The set of transistor element also includes an anti-propagation region of the first doping type between the first well and the second well

STACKED FET SIDEWALL STRAP CONNECTIONS BETWEEN GATES (17706675)

Inventor Chen Zhang

Brief explanation

The abstract describes a new method of connecting the gates of stacked transistors using sidewall straps. Stacked transistors are a type of electronic component that are arranged on top of each other. The method involves using a dielectric material to prevent direct contact between the gates of the transistors. Instead, a sidewall strap is used to connect the gates of the transistors, allowing for better communication between them. This new method could potentially improve the performance and efficiency of electronic systems.

Abstract

A set of stacked transistors, system, and method to connect the gates of stacked field-effect transistors through sidewall straps. The set of stacked transistors may include a first transistor including a first gate. The set of stacked transistors may also include a second transistor including a second gate, where the second transistor is above the first transistor. The set of stacked transistors may also include a dielectric preventing direct contact between the first gate and the second gate. The set of stacked transistors may also include a first sidewall strap proximately connected to the first gate and the second gate, where the first sidewall strap connects the first transistor and the second transistor.

SELF-ALIGNED BACKSIDE TRENCH EPITAXY FOR LOW CONTACT RESISTIVITY (17656890)

Inventor Ruilong Xie

Brief explanation

The abstract describes a structure consisting of two nanosheet stacks, each with a source drain. The first source drain is connected to the first nanosheet stack, while the second source drain is adjacent to the second nanosheet stack. A carrier wafer is bonded to the upper surface of the structure. There is a bottom source drain contact on the bottom surface of the first source drain, and a top source drain contact on the upper surface of the second source drain. The abstract also mentions the presence of an epitaxial region between the bottom source drain contact and the first source drain. The process of forming the structure involves creating the nanosheet stacks, attaching the carrier wafer, and adding the source drain contacts.

Abstract

A first and a second nanosheet stack, a first source drain to the first nanosheet stack, a carrier wafer bonded to an upper surface, a bottom source drain contact located on a bottom surface of the first source drain, an epitaxial region between the bottom source drain contact and the first source drain, a second source drain adjacent to the second nanosheet stack and a top source drain contact located on an upper surface of the second source drain, the bottom source drain contact and the top source drain contact on opposite sides. Forming a first and a second nanosheet stack, forming an upper top source drain contact to first source drain adjacent to the first nanosheet stack, bonding a carrier wafer to an upper surface and forming a bottom source drain contact to a lower horizontal surface of a second source drain adjacent to the second nanosheet stack.

STACKED FIELD EFFECT TRANSISTORS WITH REDUCED GATE-TO-DRAIN PARASITIC CAPACITANCE (17709628)

Inventor Shogo Mochizuki

Brief explanation

The abstract describes a type of transistor called an inner field effect transistor (FET) and an outer FET. The inner FET has a source, a drain, and a group of nanosheet channel structures that connect the source and drain. The outer FET also has a source, a drain, and nanosheet channel structures that connect them. There is an isolation region between the inner and outer FETs. A metal gate stack is located between the source and drain of both the inner and outer FETs, surrounding the nanosheet channel structures. The metal gate stack includes a dielectric region next to the isolation region.

Abstract

An inner field effect transistor has an inner source, an inner drain, and a group of inner nanosheet channel structures interconnecting the inner source and the inner drain. An outer field effect transistor has an outer source, an outer drain, and a group of outer nanosheet channel structures interconnecting the outer source and the outer drain. An isolation region is located between the inner field effect transistor and the outer field effect transistor. A metal gate stack is located between the inner source and inner drain and between the outer source and the outer drain. The metal gate stack at least partially surrounds the inner and outer nanosheet channel structures. The metal gate stack has a dielectric region adjacent the isolation region.

HIGH ASPECT RATIO CONTACT STRUCTURE WITH MULTIPLE METAL STACKS (17657006)

Inventor Junli Wang

Brief explanation

This abstract describes a contact structure that is formed within a dielectric material. The structure has two parts - a top portion and a bottom portion. The top portion has a tapering profile towards the bottom portion. Inside the top portion, there is a first metal stack surrounded by an inner spacer. Inside the bottom portion, there is a second metal stack. The width of the bottom portion is larger than the minimum width of the top portion.

Abstract

A high aspect ratio contact structure formed within a dielectric material includes a top portion and a bottom portion. The top portion of the contact structure includes a tapering profile towards the bottom portion. A first metal stack surrounded by an inner spacer is located within the top portion of the contact structure and a second metal stack is located within the bottom portion of the contact structure. A width of the bottom portion of the contact structure is greater than a minimum width of the top portion of the contact structure.

OPTIMIZING MOUNTING POINTS FOR COAXIAL RF CONNECTORS (17708632)

Inventor PHILLIP V. MANN

Brief explanation

The abstract describes systems that are designed to optimize the placement of coaxial RF connectors. These systems include a printed circuit board (PCB) with a coaxial RF connector, a faceplate with an opening to accommodate the connector, and a bushing that holds the connector in place within the opening. The purpose of these systems is to ensure proper positioning and secure mounting of the coaxial RF connectors.

Abstract

Systems for optimizing mounting points for coaxial RF connectors, including a printed circuit board (PCB) comprising a coaxial radio frequency (RF) connector; a faceplate comprising an opening adapted to receive the coaxial RF connector; and a bushing positioned within the opening, wherein the coaxial RF connector is positioned within the bushing.

METHOD TO LIMIT THE TIME A SEMICONDUCTOR DEVICE OPERATES ABOVE A MAXIMUM OPERATING VOLTAGE (17657989)

Inventor Adam Benjamin COLLURA

Brief explanation

The abstract describes a method and system for identifying and addressing power or voltage fluctuations in specific areas of a semiconductor device. When a region of the device experiences reduced power draw and a resulting voltage spike that could shorten the device's lifespan, the system activates circuits or current generators in that region to draw additional power and lower the voltage spike. This helps reduce the number of devices that need to be discarded due to voltage violations and improves the reliability and lifespan of the device.

Abstract

The method and systems described herein provide for identifying and mitigating undesirable power or voltage fluctuations in regions of a semiconductor device. For example, embodiments include detecting a region, such as an individual processor, of a processor chip is exhibiting a reduced power draw and a resulting localized voltage spike (e.g., a spike that exceeds Vmax) that would accelerate overall device end-of-life (EOL). The described systems respond by activating circuits or current generators located in the given region to draw additional power via a protective current. The protective current lowers the local voltages spikes back to within some pre-specified range (e.g., below a Vmax). The resulting reduction in the time above Vmax in testing reduces the number of devices that will need to be discarded due to Vmax violations as well as increases the expected reliability and lifespan of the device in operation.

SECURE MODIFICATION OF CONTROLLED DEVICES (17656680)

Inventor Eric J. Campbell

Brief explanation

This abstract describes a system and method for securely controlling a device from another device. When a user tries to make changes to the device, a request is generated and sent to a controlling device. The request contains information about the desired modification. The controlling device analyzes the request and decides how to respond. The response is encrypted and sent back to the device. The device then decrypts the response and carries out the indicated response. The encryption and decryption keys are stored in the devices themselves, so the device doesn't need to receive any sensitive information to decrypt the response.

Abstract

A system and method of securely controlling a device from another device. The user of the device attempts to modify the device in some way. In response to the attempted modification a request is generated and sent to a controlling device. The request includes information related to the desired modification. The controlling device analyzes the request and a determination on how to respond to the request is made. This response is encrypted at the controlling device and transmitted to the device. The device then decrypts the response and implements the indicated response to the request. The encryption and decryption keys are burned into the corresponding devices such that information needed to decrypt the response is not transmitted to the device.

QUANTUM SAFE KEY EXCHANGE SCHEME (18330410)

Inventor Richard Victor Kisley

Brief explanation

The abstract describes a computer-based method for executing a hybrid quantum safe key exchange system. This method involves several steps, including retrieving an authenticated random value from a trusted source, generating two different Z values using elliptic curve cryptography, deriving a shared key using the authenticated random value and the Z values, decrypting the authenticated random value using a quantum safe algorithm, and finally deriving the shared key again using the authenticated random value and the second Z value.

Abstract

Aspects of the invention include a computer-implemented method of executing a hybrid quantum safe key exchange system. The computer-implemented method includes initially retrieving an authenticated random value from a trusted source, generating a first Z value using a first elliptic curve (EC) private key and a first certified form of an EC public key with an EC Diffie-Hellman (ECDH) algorithm, deriving a shared key using the authenticated random value and the first Z value with a key derivation function, decrypting the authenticated random value using a quantum safe algorithm (QSA) private key, generating a second Z value using a second EC private key and a second certified form of the EC public key with the ECDH algorithm and deriving the shared key using the authenticated random value and the second Z value with the key derivation function.

KEY IMPORT WITH HYBRID CRYPTOGRAPHY (17657193)

Inventor Vaijayanthimala K. Anand

Brief explanation

This abstract describes a method for encrypting imported key material using a combination of classical cryptography and quantum-safe cryptography. When a user system requests to import key material, two public keys are sent to the user system - one for classical cryptography and one for quantum-safe cryptography. These public keys are retrieved from a hardware security module (HSM). The user system then encrypts the key material using both public keys, creating hybrid-encrypted key material. This hybrid-encrypted key material, which is partially encrypted by at least one of the public keys, is then sent back to the HSM.

Abstract

Hybrid encryption of imported key material is provided. A request to import key material is received from a user system. In response to the request, two public keys are sent to the user system. The two public keys include a classical cryptography (CC) public key and a quantum-safe cryptography (QSC) public key. At least one public key of the two public keys is retrieved from a hardware security module (HSM). Hybrid-encrypted key material is received from the user system. The hybrid-encrypted key material is key material that has been encrypted using the two public keys. The key material, at least partially encrypted by the at least one public key, is sent to the HSM.

VEHICLE AND POWER MANAGEMENT USING POWER OVER ETHERNET DEVICES (17708396)

Inventor Aaron K. Baughman

Brief explanation

This abstract describes a server that regulates power from a Power-over-Ethernet switch to multiple vision sensors. The server evaluates the contribution of each sensor to the efficiency of the vision system. It also receives information about any degradation in the sensors' performance. Based on this information, the server estimates the amount of power needed to alleviate the degradation. If the total power supplied exceeds the available power from the switch, the server prioritizes and regulates power to each sensor in real-time according to their contribution to the system's efficiency.

Abstract

A server for regulating power from a Power-over-Ethernet switch to a plurality of vision sensors includes the following operations. An evaluation of individual contributions that each of the plurality of vision sensors makes to operational efficiency of the vision system is performed. Information indicative of a degradation condition to the plurality of vision sensors is received from the plurality of vision sensors. An amount of power needed to be supplied from the switch to alleviate the degradation condition of the plurality of vision sensors is estimated based upon the information indicative of the degradation condition. A determination is made that a total amount of power supplied from the switch exceeds an available amount of power capable of being supplied from the switch. Power from the switch to the plurality of vision sensors is individually regulated in real-time using a prioritization determined according to the evaluation.

LOCAL ARRANGEMENT OF REMOTE DEPLOYMENT (17657952)

Inventor Guanqin Zhang

Brief explanation

The abstract describes a computer-based method for setting up a remote deployment. It involves receiving a request to connect with a remote virtualization entity proxy, establishing a network tunnel between a local system and the remote proxy, and arranging components from the remote proxy into a local virtualization entity on the local system using the network tunnel.

Abstract

A computer-implemented method for local arrangement of remote deployment is provided according to embodiments of the present disclosure. In this method, a starting request to connect with a remote virtualization entity proxy can be received. A network tunnel can be initiated between a local system and the remote virtualization entity proxy. Then, at least one component in the remote virtualization entity proxy can be arranged into a local virtualization entity in the local system via the network tunnel.

ENHANCING SOFTWARE APPLICATION HOSTING IN A CLOUD ENVIRONMENT (18310972)

Inventor Sudheesh S Kairali

Brief explanation

This abstract describes a method to optimize server connection timeout errors in a cloud environment. The approach involves creating a knowledge corpus based on historical data and predicting the criticality of a transaction based on contextual situations. The connection timeout range of the transaction is dynamically adjusted based on the predicted criticality and contextual situations. The method also involves analyzing timeout errors on a remote server and adjusting timeout values accordingly. If a transaction receives a timeout error, a recommended timeline is provided for when the transaction can be reinitiated.

Abstract

In an approach to optimize server connection timeout errors in a cloud environment, embodiments create a knowledge corpus associated with connection timeout patterns based on historical learning of transaction parameters and predicts a criticality of a transaction based on one or more identified contextual situations. Further, embodiments dynamically adjust a connection timeout range of the transaction based on the predicted criticality and one or more identified contextual situations of the transaction, and selectively identify a connection timeout range for the transaction based on an evaluation of the one or more contextual situations. Additionally, embodiments analyze generated timeout errors on a remote server from within a service mesh, and adjust timeout values of the transaction based on the analyzed generated timeouts errors. Responsive to the transaction receiving a timeout error, embodiments output a recommended timeline detailing when the transaction can be reinitiated.

COMPLIANCE MECHANISMS IN BLOCKCHAIN NETWORKS (18330433)

Inventor Petr Novotny

Brief explanation

The abstract describes a process in a blockchain network where a node can agree to accept a compliance module from an authority. This compliance module helps the node verify the compliance of an operation. Once the node receives an operation, it uses the compliance module to check if the operation meets the required compliance standards. If it does, the node adds the verified operation to a ledger on the blockchain network.

Abstract

A node in a blockchain network may agree, on an authority accept a compliance module from the authority, accept the compliance module. The node may also receive an operation, verify a compliance of the operation based on the compliance module, add the verified operation to a ledger on the blockchain network.

ROUTING PREFERENCE BASED COMMUNICATION TO A CLOSED GROUP HIERARCHY (17656953)

Inventor Jignesh K Karia

Brief explanation

This abstract describes a method, computer system, and computer program for directing messages. The system involves a computer that receives a registration of members organized into a closed group hierarchy. The computer also receives a notification of a change in the environment of the group hierarchy. Additionally, the computer receives a message from an external device that relates to the changed element. The computer then selects a member of the group hierarchy based on established message routing guidelines and transmits the message to that selected member.

Abstract

A method, computer system, and a computer program product for message directing are provided. A first computer receives a registration of members organized into a first closed group hierarchy. The first computer receives a notification of a sensed change of an element in an environment of the first closed group hierarchy. The first computer receives a first message from an external device. The first message relates to the changed element. The first computer selects a first member of the first closed group hierarchy for receipt of the first message. The selecting is based on message routing guidelines established for the first closed group hierarchy. In response to receiving the notification of the sensed change, the first computer transmits the first message to the selected first member of the first closed group hierarchy.

BIDIRECTIONAL RING-BASED INTERCONNECTION NETWORKS FOR MULTIPROCESSORS (17708073)

Inventor Avery Francois

Brief explanation

This abstract describes a technology that processes commands on a multiprocessor chip with multiple interconnected nodes. The chip has a clockwise ring network and a counterclockwise ring network. When a command is received for execution and both ring networks are available, the command is executed bidirectionally. This involves transmitting warning signals on both ring networks, followed by transmitting the command on each network after a certain number of clock cycles.

Abstract

Embodiments include processing commands on multiprocessor chip having a plurality of nodes that are interconnected via a clockwise ring network and a counterclockwise ring network. Aspects include receiving a command for execution and based at least in part on a determination that the clockwise ring network and the counterclockwise ring network are both available for transmission, performing a bidirectional execution of the command. The bidirectional execution includes transmitting a first warning signal on the clockwise ring network and a second warning signal on the counterclockwise ring network, transmitting the command on the clockwise ring network a first number of clock cycles after the first warning signal, and transmitting the command on the counterclockwise ring network a second number of clock cycles after the second warning signal.

DATA TRANSMISSION FLOW CONTROL REGIME (17709512)

Inventor Giora Biran

Brief explanation

The abstract describes a flow control system that uses speculative credit. In this system, if an agent does not receive credit from a downstream agent within a certain time frame, it can return speculative credit to an upstream agent. This allows the upstream agent to continue its operations, even if it is not currently able to perform the tasks represented by the speculative credit.

Abstract

A credit-based flow control system can utilize speculative credit. If an agent has not received a credit return from a downstream agent for a given period of time, the agent can return speculative credit to an upstream agent. This way, even if the agent is not currently capable of performing operations represented by the speculative credit, the upstream agent can be enabled to proceed with operations.

PROACTIVE AUTO-SCALING (17657268)

Inventor Yi Ming Wang

Brief explanation

This abstract describes a method for automatically adjusting the resources allocated to a group of services in a container platform. The approach involves collecting usage data from the services and using it to predict future access patterns and resource needs. A dynamic correlation topology is then created based on this information, which helps identify other services that are related to the original ones. When a service request exceeds a certain threshold, the system automatically scales up the resources allocated to the services and their associated services.

Abstract

In an approach for proactive service group based auto-scaling, a processor collects usage data generated in one or more services in a container platform. A processor predicts access situation and resource utilization of the one or more services based on the usage data. A processor constructs a dynamic correlation topology among the one or more services based on the access situation and resource utilization. A processor identifies associated services correlated with the one or more services based on the dynamic correlation topology. A processor, in response to a service request exceeding a pre-set threshold, expands the one or more services and associated services.

Consolidating structured and unstructured security and threat intelligence with knowledge graphs (18205681)

Inventor Youngja Park

Brief explanation

This abstract describes an automated method for processing security events. It involves creating a knowledge graph using security information from structured data sources. Additional information is then extracted from unstructured data sources, such as text, which includes the entities identified in the structured data. Relationships involving these entities are extracted from the text to generate new entities and relationships. The initial knowledge graph is then updated with this new information to create a consolidated version. This updated version is used to process security event data.

Abstract

An automated method for processing security events. It begins by building an initial version of a knowledge graph based on security information received from structured data sources. Using entities identified in the initial version, additional security information is then received. The additional information is extracted from one or more unstructured data sources. The additional information includes text in which the entities (from the structured data sources) appear. The text is processed to extract relationships involving the entities (from the structured data sources) to generate entities and relationships extracted from the unstructured data sources. The initial version of the knowledge graph is then augmented with the entities and relationships extracted from the unstructured data sources to build a new version of the knowledge graph that consolidates the intelligence received from the structured data sources and the unstructured data sources. The new version is then used to process security event data.

CLOUD FINANCIAL LOAD OPTIMIZATION BASED ON POWER AND THERMAL STATISTICS AGGREGATION (17708487)

Inventor Franck Excoffier

Brief explanation

This abstract describes an approach for optimizing server-based loads between data centers. The approach involves receiving data from a hardware abstraction layer associated with servers in multiple data centers. The data is then filtered to focus on the data centers with the highest power usage and thermal state conditions. The filtered data is aggregated into performance data groups based on their association with a specific data center. Two-ratio statistics are generated from these aggregated groups, and a data center score is calculated based on these statistics. The approach then selects data center sites with the lowest scores and initiates a request to transfer server-based loads from the servers associated with the filtered data to these selected data center sites.

Abstract

An approach for optimizing server-based loads between data centers. The approach receives data from a hardware abstraction layer (HAL) associated with servers in a plurality of data centers. The approach filters the data associated with a portion of the data centers having the highest power usage and thermal state conditions. The approach aggregates the filtered data into performance data groups based on association with a data center. The approach creates two-ratio statistics of the aggregated groups. The approach generates a data center score based on the two-ratio statistics. The approach selects data center sites with the lowest scores. The approach initiates a request to transfer server-based loads from the servers associated with the filtered data to the data center sites with the lowest scores.

COLLABORATIVE MONITORING OF LOCATION CONDITIONS (17690047)

Inventor Denise Bell

Brief explanation

This abstract describes a computer-based method for monitoring the condition of a specific location. The method involves storing monitoring records related to different segments of the location. These records are collected by mobile computing devices as they pass through each segment. The method also involves receiving monitoring records from other mobile computing devices. Each monitoring record contains values that indicate the condition of specific positions within the corresponding segment. The method includes transmitting the stored monitoring records to target mobile computing devices. The monitoring records are then filtered based on their homogeneity. Finally, the filtered monitoring records are uploaded to validate them and determine condition indicators for each segment based on the validated records.

Abstract

A computer-implemented method for monitoring a condition of a location is disclosed. This method includes storing monitoring records relating to segments of the location comprising one or more monitoring records being collected by the mobile computing device passing through the segment and monitoring records being received from a source mobile computing device of the mobile computing devices, each of the monitoring records comprising monitoring values indicative of a condition of corresponding positions of the corresponding segment, transmitting the monitoring records of each segment being stored to a target mobile computing devices, filtering the monitoring records of each segment being stored according to a homogeneity thereof, and uploading the monitoring records of each segment being filtered to validate the monitoring records of each segment according to a matching thereof and to determine at least one condition indicator of each segment according to the corresponding monitoring records being validated.

LOCATION BASED ATTESTATION (17708013)

Inventor Grant Douglas Miller

Brief explanation

The abstract describes a computer method for managing access requests based on the location of a user's device. When a user initiates an access request from their device, the method receives the location data of the device. It then requests attestation from a trusted device registered to the user, which includes its own location data. The method compares the location data of the user's device to the registered device's location data and issues an authentication status based on the comparison. The abstract also mentions that there is a computer program product and computer system corresponding to this method.

Abstract

A computer implemented method for managing access requests based on user device location includes receiving a user initiated access request from a first device of the user, receiving location data of the first device, requesting attestation of a registered device of the user from a trusted geocoded device, receiving an attestation token for the registered device of the user from the trusted geocoded device, wherein the attestation token includes location data for the registered device, comparing the received location data of the first device to the location data of the registered device, and issuing an authentication status based on the comparison of the received location data of the first device to the determined location data of the second device of the user. A computer program product and computer system corresponding to the method are also disclosed.

TUNABLE TOLERANCE STACK-COMPLIANT LATCHING (17710994)

Inventor Arthur J. Higby

Brief explanation

The abstract describes a latch assembly that consists of a lever arm attached to a pivot point. The pivot point has a cam with a slot. There is also a load mechanism that applies a force on the pivot point to keep the lever arm in a specific position. The load mechanism is designed to apply the force within a certain range of operation for the latch assembly.

Abstract

A latch assembly includes a lever arm affixed to a latch pivot point of rotation with a cam having a connecting slot. A load mechanism is configured to apply a force on the latch pivot point to retain the lever arm in a first position. The load mechanism is tuned to apply the force along a tolerance range of operation of the latch assembly.

HIGH DENSITY STACKED VERTICAL TRANSISTOR STATIC RANDOM ACCESS MEMORY STRUCTURE (17657446)

Inventor Brent A Anderson

Brief explanation

The abstract describes a semiconductor structure that includes a static random access memory (SRAM) cell. The SRAM cell is divided into two sections, each containing different transistors. The layout of the SRAM cell is non-rectangular, with one pass-gate transistor located at one end and another pass-gate transistor located at the opposite end.

Abstract

Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a static random access memory (SRAM) cell. The SRAM cell may include a first section of the SRAM cell with a first pull-up transistor, first pull-down transistor, and first pass-gate transistor. The SRAM cell may include a second section of the SRAM cell with a second pull-up transistor, second pull-down transistor, and second pass-gate transistor. The first section of the SRAM cell and the second section of the SRAM cell may be arranged in a non-rectangular cell layout with the first pass-gate located at a first end of the non-rectangular cell layout and the second pass-gate at a second end of the non-rectangular cell layout opposite the first end.

NANOSHEET PULL-UP TRANSISTOR IN SRAM (17657961)

Inventor HUIMEI ZHOU

Brief explanation

The present invention is about a static random-access-memory (SRAM) device. This device consists of two sets of nanosheets used in transistors. The first set is used in an n-type transistor, while the second set is used in a p-type transistor. The width of the second set of nanosheets is wider than the width of the first set. In one embodiment, the p-type transistor functions as a pull-up transistor, while the n-type transistor can be used as a pull-down transistor or a pass-gate transistor. The invention also includes a method for manufacturing this SRAM device.

Abstract

Embodiments of present invention provide a static random-access-memory (SRAM) device. The SRAM device includes a first set of nanosheets used in an n-type transistor; and a second set of nanosheets with one or more nanosheets of the second set of nanosheets used in a p-type transistor, wherein a width of the second set of nanosheets is wider than a width of the first set of nanosheets. In one embodiment the p-type transistor is used as a pull-up transistor and the n-type transistor is used as a pull-down transistor or a pass-gate transistor. A method of manufacturing the SRAM device is also provided.

SOLID-STATE SWITCH (17693340)

Inventor Guy M. Cohen

Brief explanation

The abstract describes a structure called a solid-state switch that consists of two different materials with programmable electrical resistance. The first material has a high resistance after a certain type of programming pulse and a low resistance after a different type of programming pulse. The second material behaves in the opposite way, with a high resistance after the second type of programming pulse and a low resistance after the first type of programming pulse. The switch also includes three contacts that connect to the ends of both materials.

Abstract

A solid-state switch structure including a first solid-state material having a programable electrical resistance comprising a high electrical resistance obtained following a first type programming pulse and a low electrical resistance obtained following a second type programming pulse, a second solid-state material having a programable electrical resistance comprising a high electrical resistance obtained following said second type programming pulse and a low electrical resistance obtained following said first type programming pulse, a first contact made to a first end of said first solid-state material, a second contact made to a first end of said second solid-state material, a third contact made to a second end of said first solid-state material and to a second end of said second solid-state material.

TETRAGONAL HALF METALLIC HEUSLER COMPOUNDS (17710438)

Inventor SERGEY FALEEV

SUPERCONDUCTING SILICON TRANSISTOR AND FABRICATION THEREOF (17707898)

Inventor Matthias Mergenthaler

Brief explanation

The abstract describes a device made of superconducting materials. It consists of a substrate, which is a base material. On opposite sides of a silicon channel and on top of the substrate, there are two silicides. These silicides are in contact with two superconducting contacts. A dielectric material is placed between these contacts. On top of the dielectric, there is a gate.

Abstract

A superconductor device includes a substrate. There is a first silicide and a second silicide located on opposite sides of a silicon channel and on top of the substrate. A first superconducting contact is in contact with the first silicide. A second superconducting contact is in contact with the second silicide. A dielectric is located between the first and second superconducting contacts. A gate is on top of the gate dielectric.

SUPERCONDUCTING QUBIT CAPACITANCE AND FREQUENCY OF OPERATION TUNING (18063722)

Inventor Douglas M. Gill

Brief explanation

This abstract describes a method for adjusting the resonance frequency of a qubit in a quantum mechanical device. The method involves using a substrate with a qubit on its frontside, which includes capacitor pads. By removing substrate material from the backside of the substrate, specifically in the area opposite the qubit, the capacitance around the qubit is altered. This alteration allows for the adjustment of the resonance frequency of the qubit.

Abstract

A method for adjusting a resonance frequency of a qubit in a quantum mechanical device includes providing a substrate having a frontside and a backside, the frontside having at least one qubit formed thereon, the at least one qubit comprising capacitor pads; and removing substrate material from the backside of the substrate at an area opposite the at least one qubit to alter a capacitance around the at least one qubit so as to adjust a resonance frequency of the at least one qubit.