Huawei technologies co., ltd. (20240125850). Automatic Test Pattern Generation-Based Circuit Verification Method and Apparatus simplified abstract
Contents
- 1 Automatic Test Pattern Generation-Based Circuit Verification Method and Apparatus
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 Automatic Test Pattern Generation-Based Circuit Verification Method and Apparatus - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
Automatic Test Pattern Generation-Based Circuit Verification Method and Apparatus
Organization Name
Inventor(s)
Huiling Zhen of Hong Kong (CN)
Mingxuan Yuan of Hong Kong (CN)
Automatic Test Pattern Generation-Based Circuit Verification Method and Apparatus - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240125850 titled 'Automatic Test Pattern Generation-Based Circuit Verification Method and Apparatus
Simplified Explanation
The patent application describes an automatic test pattern generation-based circuit verification method that involves determining logic cones, generating a CNF, and detecting target lines based on specified conditions.
- Determining a first logic cone from a fan-out logic cone corresponding to the target line
- Determining a second logic cone from a fan-in logic cone based on the first logic cone
- Generating a CNF based on the first and second logic cones to detect the target line
- Determining a verification result based on the detection result meeting specified conditions
Potential Applications
This technology can be applied in the field of integrated circuit design and testing to improve the efficiency and accuracy of circuit verification processes.
Problems Solved
1. Streamlining circuit verification processes 2. Enhancing the reliability of circuit testing
Benefits
1. Automated test pattern generation 2. Improved detection of target lines 3. Enhanced verification results
Potential Commercial Applications
Optimizing circuit design and testing processes for semiconductor companies
Possible Prior Art
Previous methods of circuit verification may have involved manual test pattern generation and detection processes, which could be time-consuming and less accurate compared to the automated approach described in this patent application.
Unanswered Questions
How does this method compare to existing circuit verification techniques in terms of efficiency and accuracy?
The article does not provide a direct comparison with traditional circuit verification methods to assess the advantages of the proposed approach.
What specific conditions are considered in determining the verification result of the target line?
The patent application mentions specified conditions for determining the verification result, but the exact criteria are not elaborated upon in the abstract.
Original Abstract Submitted
an automatic test pattern generation-based circuit verification method, comprises: determining a to-be-detected first logic cone from a fan-out logic cone corresponding to the target line; determining, based on the first logic cone, a to-be-detected second logic cone from a fan-in logic cone corresponding to the target line; generating a first cnf based on the first logic cone and the second logic cone, and detecting the target line by using the first cnf to obtain a first detection result; and if the first logic cone is a partial region in the fan-out logic cone, and the first detection result meets a first specified condition corresponding to the first logic cone, determining a first verification result of the target line based on the first detection result.
