Huawei technologies co., ltd. (20240121942). MEMORY AND FORMING METHOD THEREOF, AND ELECTRONIC DEVICE simplified abstract
Contents
- 1 MEMORY AND FORMING METHOD THEREOF, AND ELECTRONIC DEVICE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 MEMORY AND FORMING METHOD THEREOF, AND ELECTRONIC DEVICE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
MEMORY AND FORMING METHOD THEREOF, AND ELECTRONIC DEVICE
Organization Name
Inventor(s)
Weiliang Jing of Shanghai (CN)
Kailiang Huang of Shenzhen (CN)
MEMORY AND FORMING METHOD THEREOF, AND ELECTRONIC DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240121942 titled 'MEMORY AND FORMING METHOD THEREOF, AND ELECTRONIC DEVICE
Simplified Explanation
The memory described in the patent application consists of storage units formed on a substrate, each including a transistor and a capacitor connected to the transistor. The transistor comprises a gate, a semiconductor layer, a first electrode, a second electrode, and a gate dielectric layer. The first electrode and the second electrode are arranged in a first direction, with the gate located between them. The semiconductor layer is located on one of two opposite sides of the gate in a second direction, parallel to the substrate. The semiconductor layer is electrically connected separately to the first electrode and the second electrode, with the gate and the semiconductor layer isolated from each other by the gate dielectric layer.
- The memory includes storage units with transistors and capacitors.
- Each transistor has a gate, semiconductor layer, first electrode, second electrode, and gate dielectric layer.
- The first and second electrodes are arranged in a first direction, with the gate in between.
- The semiconductor layer is located on one side of the gate in a second direction, parallel to the substrate.
- The semiconductor layer is electrically connected to the electrodes separately, with isolation provided by the gate dielectric layer.
Potential Applications
This technology could be applied in:
- Computer memory systems
- Mobile devices
- Embedded systems
Problems Solved
This technology helps address:
- Increasing demand for higher memory capacity
- Improving memory performance and reliability
Benefits
The benefits of this technology include:
- Enhanced memory storage capabilities
- Improved data processing speed
- Increased efficiency in memory operations
Potential Commercial Applications
The potential commercial applications of this technology could be in:
- Consumer electronics
- Data centers
- Automotive industry
Possible Prior Art
One possible prior art for this technology could be:
- Traditional memory storage units with transistors and capacitors
Unanswered Questions
How does this technology compare to existing memory technologies?
This article does not provide a direct comparison with existing memory technologies, making it difficult to assess its advantages over current solutions.
What are the potential limitations or challenges in implementing this technology on a large scale?
The article does not address any potential limitations or challenges that may arise when implementing this technology on a large scale, leaving room for further exploration in this area.
Original Abstract Submitted
a memory comprises a substrate and a plurality of storage units formed on the substrate. each of the storage units includes a transistor and a capacitor electrically connected to the transistor. the transistor includes a gate, a semiconductor layer, a first electrode, a second electrode, and a gate dielectric layer. the first electrode and the second electrode are arranged in a first direction. the gate is located between the first electrode and the second electrode. the semiconductor layer is located on one of two opposite sides of the gate in a second direction. the semiconductor layer is electrically connected separately to the first electrode and the second electrode, the gate and the semiconductor layer are isolated from each other by the gate dielectric layer, and the second direction is a direction parallel to the substrate.
