CLOCK DRIVER FOR TIME-INTERLEAVED DIGITAL-TO-ANALOG CONVERTER: abstract simplified (17654916)

Method for Providing Clock Signals to Sub-DACs

This method involves dividing an input clock signal into two separate signals, referred to as the first divided clock signal and the second divided clock signal. These divided clock signals are then used to gate the input clock signal, resulting in the generation of two drive clock signals.

The first drive clock signal is created by gating the input clock signal using the first divided clock signal. This first drive clock signal is then inputted into the clock input of the first sub-DAC.

Similarly, the second drive clock signal is generated by gating the input clock signal using the second divided clock signal. This second drive clock signal is then inputted into the clock input of the second sub-DAC.

In summary, this method provides a way to generate and provide separate drive clock signals to two sub-DACs by dividing and gating an input clock signal.