View source for BIT LINE AND WORD LINE CONNECTION FOR MEMORY ARRAY: abstract simplified (18332058)

*This abstract for appeared for patent application  number 18332058 Titled 'BIT LINE AND WORD LINE CONNECTION FOR MEMORY ARRAY'

==Simplified Explanation==

The abstract describes a type of integrated chip that includes multiple layers of conductive interconnect structures. The first layer is located on top of a substrate, and a memory stack is placed on this layer. A second layer of conductive interconnect structures is positioned between the opposing sidewalls of the first layer. Finally, a third layer of conductive interconnect structures is placed on top of the first layer, with its top surface directly above the second layer.


==Original Abstract Submitted==

Various embodiments of the present application are directed towards an integrated chip including a first conductive interconnect structure overlying a substrate. A first memory stack is disposed on the first conductive interconnect structure. A second conductive interconnect structure overlies the first memory stack. The second conductive interconnect structure is spaced laterally between opposing sidewalls of the first conductive interconnect structure. A third conductive interconnect structure is disposed on the first conductive interconnect structure. A top surface of the third conductive interconnect structure is vertically above the second conductive interconnect structure.