Apple inc. (20240097937). SIGNALING OF TIME FOR COMMUNICATION BETWEEN INTEGRATED CIRCUITS USING MULTI-DROP BUS simplified abstract

SIGNALING OF TIME FOR COMMUNICATION BETWEEN INTEGRATED CIRCUITS USING MULTI-DROP BUS

Organization Name

apple inc.

Inventor(s)

Helena Deirdre O'shea of San Jose CA (US)

Matthias Sauer of San Jose CA (US)

Jorge L. Rivera Espinoza of San Jose CA (US)

SIGNALING OF TIME FOR COMMUNICATION BETWEEN INTEGRATED CIRCUITS USING MULTI-DROP BUS - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240097937 titled 'SIGNALING OF TIME FOR COMMUNICATION BETWEEN INTEGRATED CIRCUITS USING MULTI-DROP BUS

Simplified Explanation

The patent application relates to including information in a data packet transmitted over a multi-drop bus to account for a time delay caused by an unsuccessful arbitration attempt. The data packet includes a data field with time delay information, allowing the receiving integrated circuit to determine when the packet would have been sent if the arbitration attempt had been successful. Additionally, the patent application includes a synchronization generator circuit that generates timing signals indicating when periodic events occur at another integrated circuit.

• Explanation of the patent:

 * Data packets include time delay information due to unsuccessful arbitration attempts.
 * Receiving integrated circuits can determine the original send time of packets.
 * Synchronization generator circuit generates timing signals for periodic events.

1. 1. 1. Potential Applications

This technology could be applied in communication systems where precise timing and synchronization are crucial, such as in industrial automation, telecommunications, and data centers.

1. 1. 1. Problems Solved

1. Addressing time delays caused by unsuccessful arbitration attempts in data transmission. 2. Ensuring accurate timing and synchronization between integrated circuits.

1. 1. 1. Benefits

1. Improved efficiency in data transmission. 2. Enhanced reliability in communication systems. 3. Simplified troubleshooting of timing issues.

1. 1. 1. Potential Commercial Applications
         1. Optimizing Data Transmission Timing in Integrated Circuits

1. 1. 1. Possible Prior Art

There may be prior art related to techniques for handling time delays in data transmission caused by arbitration attempts in multi-drop bus systems.

1. 1. 1. 1. Unanswered Questions
         2. How does the synchronization generator circuit handle variations in timing between integrated circuits?

The patent application does not provide detailed information on how the synchronization generator circuit adjusts for timing variations between integrated circuits.

1. 1. 1. 1. Are there any potential drawbacks to including time delay information in data packets?

The patent application does not discuss any potential drawbacks or limitations of including time delay information in data packets for transmission.

Original Abstract Submitted

embodiments relate to including information in a data packet transmitted by a transmitting integrated circuit (e.g., soc) to account for a time delay associated with an unsuccessful arbitration attempt to send the data packet over a multi-drop bus. the unsuccessful arbitration attempt by the integrated circuit may delay the transmission of the data packet until the multi-drop bus becomes available for the integrated circuit to send the data packet. the data packet includes a data field to include time delay information caused by the unsuccessful arbitration attempt. a receiving integrated circuit may determine the time that the data packet would have been sent out from the transmitting integrated circuit absent the unsuccessful arbitration attempt based on the delay information. embodiments also relate to a synchronization generator circuit in an integrated circuit that generates timing signals indicating times at which periodic events occur at another integrated circuit.