View source for 18543769. REDUCED ESR IN TRENCH CAPACITOR simplified abstract (Texas Instruments Incorporated)

=REDUCED ESR IN TRENCH CAPACITOR=


==Organization Name==

[[:Category:Texas Instruments Incorporated|Texas Instruments Incorporated]]


[[Category:Texas Instruments Incorporated]]

==Inventor(s)==

[[:Category:Jing Hu of Chengdu (CN)|Jing Hu of Chengdu (CN)]][[Category:Jing Hu of Chengdu (CN)]]

[[:Category:ZHI PENG Feng of Chengdu (CN)|ZHI PENG Feng of Chengdu (CN)]][[Category:ZHI PENG Feng of Chengdu (CN)]]

[[:Category:Chao Zuo of Chengdu (CN)|Chao Zuo of Chengdu (CN)]][[Category:Chao Zuo of Chengdu (CN)]]

[[:Category:Dongsheng Liu of Chengdu (CN)|Dongsheng Liu of Chengdu (CN)]][[Category:Dongsheng Liu of Chengdu (CN)]]

[[:Category:Yunlong Liu of Chengdu (CN)|Yunlong Liu of Chengdu (CN)]][[Category:Yunlong Liu of Chengdu (CN)]]

[[:Category:Manoj K Jain of Plano TX (US)|Manoj K Jain of Plano TX (US)]][[Category:Manoj K Jain of Plano TX (US)]]

[[:Category:Shengpin Yang of Chengdu (CN)|Shengpin Yang of Chengdu (CN)]][[Category:Shengpin Yang of Chengdu (CN)]]

==REDUCED ESR IN TRENCH CAPACITOR - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18543769 titled 'REDUCED ESR IN TRENCH CAPACITOR

==Simplified Explanation==

The method described in the patent application involves fabricating an integrated circuit by etching trenches in a semiconductor layer, forming a trench dielectric layer over the trenches, depositing a doped polysilicon layer within the trenches, patterning the doped polysilicon layer to form a polysilicon bridge, and directing a blanket implant of a first dopant to form a contact region extending from the first surface into the semiconductor layer.

* Etching trenches in a semiconductor layer
* Forming a trench dielectric layer over the trenches
* Depositing a doped polysilicon layer within the trenches
* Patterning the doped polysilicon layer to form a polysilicon bridge
* Directing a blanket implant of a first dopant to form a contact region

== Potential Applications ==
This technology could be applied in the manufacturing of advanced integrated circuits, particularly in the development of high-performance electronic devices.

== Problems Solved ==
This technology helps in creating reliable and efficient connections within integrated circuits, improving overall performance and functionality.

== Benefits ==
The method allows for the fabrication of complex integrated circuits with enhanced connectivity and performance, leading to improved functionality in electronic devices.

== Potential Commercial Applications ==
The technology could find applications in the semiconductor industry for the production of advanced electronic devices with high-speed performance and reliability.

== Possible Prior Art ==
One possible prior art could be the use of similar processes for fabricating integrated circuits with improved connectivity and performance.

=== Unanswered Questions ===

== How does this technology impact the overall efficiency of integrated circuits? ==
This technology improves the efficiency of integrated circuits by enhancing connectivity and reducing resistance in the circuitry, leading to better performance.

== What are the potential cost implications of implementing this technology in semiconductor manufacturing? ==
The implementation of this technology may involve initial investment in equipment and processes, but the long-term benefits in terms of improved performance and reliability could outweigh the costs.


==Original Abstract Submitted==

A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and within the trenches. The doped polysilicon layer is patterned to form a polysilicon bridge that connects to the polysilicon within the filled trenches and a blanket implant of a first dopant is directed to the polysilicon bridge and to the first surface. The blanket implant forms a contact region extending from the first surface into the semiconductor layer.



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