18539957. EMBEDDED SAR-ADC WITH LEAST SIGNIFICANT BIT SKIPPING BASED RELU ACTIVATION FUNCTION simplified abstract (Intel Corporation)
Contents
- 1 EMBEDDED SAR-ADC WITH LEAST SIGNIFICANT BIT SKIPPING BASED RELU ACTIVATION FUNCTION
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 EMBEDDED SAR-ADC WITH LEAST SIGNIFICANT BIT SKIPPING BASED RELU ACTIVATION FUNCTION - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
EMBEDDED SAR-ADC WITH LEAST SIGNIFICANT BIT SKIPPING BASED RELU ACTIVATION FUNCTION
Organization Name
Inventor(s)
Hechen Wang of Portland OR (US)
Renzhi Liu of Portland OR (US)
Richard Dorrance of Hillsboro OR (US)
Deepak Dasalukunte of Beaverton OR (US)
Brent Carlton of Portland OR (US)
EMBEDDED SAR-ADC WITH LEAST SIGNIFICANT BIT SKIPPING BASED RELU ACTIVATION FUNCTION - A simplified explanation of the abstract
This abstract first appeared for US patent application 18539957 titled 'EMBEDDED SAR-ADC WITH LEAST SIGNIFICANT BIT SKIPPING BASED RELU ACTIVATION FUNCTION
Simplified Explanation
The patent application describes technology involving a capacitor ladder, memory cells, and a successive approximation register for performing multi-bit multiply accumulate operations and digitizing the results.
- The technology includes a capacitor ladder.
- A plurality of memory cells are coupled to the capacitor ladder to control it during multi-bit multiply accumulate operations.
- A successive approximation register is coupled to the capacitor ladder to digitize the results of the multi-bit MAC operations.
Potential Applications
This technology could be applied in signal processing, image processing, and machine learning applications.
Problems Solved
This technology solves the problem of efficiently performing multi-bit multiply accumulate operations and digitizing the results in a single system.
Benefits
The benefits of this technology include improved efficiency, accuracy, and speed in performing complex mathematical operations.
Potential Commercial Applications
One potential commercial application of this technology could be in high-performance computing systems for data centers.
Possible Prior Art
One possible prior art for this technology could be similar systems used in digital signal processing applications.
Unanswered Questions
How does this technology compare to existing systems for multi-bit multiply accumulate operations?
This technology offers a more integrated and efficient solution compared to traditional methods, but further comparative analysis is needed to fully understand its advantages.
What are the potential limitations or drawbacks of implementing this technology in practical applications?
Potential limitations could include increased complexity in system design and potential challenges in scaling the technology for larger computational tasks. Further research and testing are needed to address these concerns.
Original Abstract Submitted
Systems, apparatuses and methods may provide for technology that includes a capacitor ladder, a plurality of memory cells coupled to the capacitor ladder, the plurality of memory cells to control the capacitor ladder to conduct multi-bit multiply accumulate (MAC) operations during a computation phase, and a successive approximation register (SAR) coupled to the capacitor ladder, the SAR to control the capacitor ladder to digitize results of the multi-bit MAC operations during a digitization phase.
