18538116. CONSTRUCTING HIERARCHICAL CLOCK GATING ARCHITECTURES VIA REWRITING simplified abstract (Intel Corporation)
Contents
- 1 CONSTRUCTING HIERARCHICAL CLOCK GATING ARCHITECTURES VIA REWRITING
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 CONSTRUCTING HIERARCHICAL CLOCK GATING ARCHITECTURES VIA REWRITING - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
CONSTRUCTING HIERARCHICAL CLOCK GATING ARCHITECTURES VIA REWRITING
Organization Name
Inventor(s)
Theo Drane of El Dorado Hills CA (US)
George A. Constantinides of Santa Clara CA (US)
Emiliano Morini of El Dorado Hills CA (US)
CONSTRUCTING HIERARCHICAL CLOCK GATING ARCHITECTURES VIA REWRITING - A simplified explanation of the abstract
This abstract first appeared for US patent application 18538116 titled 'CONSTRUCTING HIERARCHICAL CLOCK GATING ARCHITECTURES VIA REWRITING
Simplified Explanation
The technique described in the patent application enables the construction of hierarchical clock gating architectures using e-graph rewriting and mux tree analysis to generate simple register enable signals.
- Automated clock gating relies on mux tree analysis.
- The framework detects non-mux based opportunities for more complex clock gating signals.
Potential Applications
The technology can be applied in various fields such as integrated circuit design, computer architecture, and hardware optimization.
Problems Solved
1. Simplifies the construction of hierarchical clock gating architectures. 2. Enables automated clock gating for improved power efficiency in electronic devices.
Benefits
1. Reduces power consumption in electronic devices. 2. Enhances performance by optimizing clock gating signals. 3. Streamlines the design process for clock gating architectures.
Potential Commercial Applications
Optimizing clock gating signals can benefit companies in the semiconductor industry, consumer electronics manufacturers, and any organization looking to improve the power efficiency of their electronic devices.
Possible Prior Art
Prior art in clock gating techniques may include research papers, patents, or industry standards related to power optimization in electronic devices.
Unanswered Questions
How does this technique compare to existing clock gating methods in terms of power efficiency and performance optimization?
The article does not provide a direct comparison with existing clock gating methods, leaving uncertainty about the specific advantages of this technique over others.
What are the potential limitations or challenges in implementing hierarchical clock gating architectures using e-graph rewriting?
The article does not address any potential limitations or challenges that may arise when implementing this technique, leaving room for further exploration into the practical implications of the innovation.
Original Abstract Submitted
Described herein is a technique to enable the construction of hierarchical clock gating architectures via e-graph rewriting. Automated clock gating relies on multiplexor (mux) tree analysis and constructs simple register enable signals. A framework is provided to detect non-mux based opportunities and construct more complex clock gating signals.
